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參數資料
| 型號： | W90100F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Embedded Micro-Controller(32位嵌入式的微控制器) |
| 中文描述： | 嵌入式微控制器（32位嵌入式的微控制器） |
| 文件頁數： | 16/61頁 |
| 文件大小： | 380K |
| 代理商： | W90100F |
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W90100F
Embedded Micro-Controller
Revision 1.1
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
-16-
Publication Release Date: 10/07/97
7.2 DMA Controller
The DMA Controller megacell provides two DMA channels to support DMA transfers between 16-bit I/O
devices and main memory. The DMA mechanism will provide two different methods for performing DMA
transfers: demand-mode transfers and block-mode transfers. The DMAC hardware is responsible for
synchronizing transfers with memory or I/O devices.
When the DMAC is configured for demand mode, a device requests a DMA transfer with a request input
(DREQ1:0#). The DMAC acknowledges the requesting device with an acknowledge signal (DACK1:0#)
when the requesting device is accessed.
In block mode, DMA transfers are not requested by an external device. The DMA operation is initiated by
software and continued until terminated or suspended. The DMA operation is started when the enable bit in
the Configuration Register is set.
DMAC megacell
LETH
MODE
SSAR
TSAR
Bus
Interface
DREQ#[2]
DACK#[2]
IOR
IOW
IODATA[16]
FIGURE 7.4 DMA CONTROLLER
In programming the megacell registers, the register address is defined by the BASE register plus the
offset value.
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