- 您現在的位置：買賣IC網 > PDF目錄363904 > W91031S (WINBOND ELECTRONICS CORP) Calling Line Identifier PDF資料下載
參數資料
| 型號： | W91031S |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | Calling Line Identifier |
| 中文描述： | 來電線路識別 |
| 文件頁數： | 11/29頁 |
| 文件大小： | 274K |
| 代理商： | W91031S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
Preliminary W91031
Publication Release Date: August 2000
- 11 - Revision A1
Mode 0
(MODE = low):
The W91031 processes the FSK signal and outputs signals on the DCLK, DATA and FDRN pins.
Figure 7-7 shows the timing diagram of the 3-wire signals and the input of the FSK signal in mode 0.
For each received stop and start bit sequence, the device outputs a fixed frequency clock string of 8
pulses on the DCLK pin. Each clock rising edge occurs in the middle of each data bit. DCLK is not
generated for the stop and start bits. The DCLK pin is used as a clock driving signal for a serial to
parallel shift register or for a serial data input for a microcontroller. After the 8-bit data has been
shifted out by the device, the FDRN pin will supply a low pulse to inform the microcontroller to
process the 8-bit data.
Tip/Ring
1*
1
0
b0 b1 b2
start
b3 b4 b5 b6 b7 1*
0
b0 b1 b2 b3 b4 b5 b6 b7 1
1
0
b0
stop
start
stop
start
DATA
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
start
stop
start
stop
start
t
IDD
DCLK
FDRN
1/f
DCLK0
t
CRD
t
RL
1st byte data
2nd byte data
1st byte data
2nd byte data
* Mark bit or redundant stop bit(s), will be omitted.
Figure 7-7. Serial Data Interface Timing of FSK Demodulation in Mode 0
Mode 1
(MODE = high):
The W91031 processes the FSK signal and sets the FDRN pin low to denote the 8-bit boundary and
to indicate to the microcontroller that new data has been transmitted. FDRN will return high on the
first rising edge of DCLK. FDRN is low for half of a nominal bit time (1/2400 sec) if DCLK is not driven
high. DCLK is used to shift 8-bit data out (LSB shift first) on the rising edge. After the last bit (MSB)
has been read, additional clock pulses on DCLK are ignored. Figure 7-8 shows the timing diagram of
the 3-wire signals and the input of the FSK signal in mode 1.
相關PDF資料 |
PDF描述 |
|---|---|
| W91080 | Tone/Pulse Dialer With Handfree And Keytone Fuctions And One Number Memory(具有一個數碼存儲器免提和主鍵音功能的音頻/脈沖撥號器) |
| W91080A | Tone/Pulse Dialer With Handfree And Keytone Fuctions And One Number Memory(具有一個數碼存儲器免提和主鍵音功能的音頻/脈沖撥號器) |
| W91082N | Tone Generator With μC Serial Interface(具有微控制器接口的音頻發生器) |
| W91312A | Tone/Pulse Dialer With Redial Function(具有重撥功能的音頻/脈沖撥號器) |
| W91312 | Tone/Pulse Dialer With Redial Function(具有重撥功能的音頻/脈沖撥號器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W91031SG | 功能描述:IC CALL LINE IDENT 24-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| W91031SG (SA5825) TR | 制造商:Nuvoton Technology Corp 功能描述:FSK DECORDER WITH CALL ON WAIT |
| W91031SG T&R | 制造商:Nuvoton Technology Corp 功能描述:IC CALL LINE IDENT 24-SOIC |
| W91031SG T&R | 功能描述:IC CALL LINE IDENT 24-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| W91040 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。