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參數(shù)資料
| 型號(hào)： | W9330F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 無(wú)繩電話/電話 |
| 英文描述： | Code Division Spread Spectrum Cordless Telephone Controller(具有編碼分劃和擴(kuò)展頻普技術(shù)的無(wú)繩電話控制器) |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 18/26頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | W9330F |
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Preliminary W9330F
- 18 -
Address 01: Command 2, write only. default: 00000000
0
FLIP_TX
FLIP_RX
SUBE
TE
RE
M/S
T/N
Bit 7: Reserved. Must be zero when writing to this register.
Bit 6: When this bit is set, the TX_DATA output pin has reversed polarity.
Bit 5: When this bit is set, the RX_DATA input pin is interpreted with reversed polarity.
Bit 4: Subframe enable. If SUBE and either TE or RE is set, an interrupt is generated at the end of
each transmit or receive subframe, depending on TE and RE. If SUBE is clear while either TE or RE
is set, an interrupt is generated only at the end of each full data frame.
Bit 3: Transmit-end enable bit. Setting this bit would enable an interrupt to be generated at the end of
each transmit frame or subframe.
Bit 2: Receive-end enable bit. Setting this bit would enable an interrupt to be generated at the end of
each receive frame or subframe.
Bit 1 is the Master/Slave select bit. The device functions as a master if this bit is set. It functions as a
slave if this bit is cleared.
Bit 0 is the Test/Normal mode select bit. This bit must be cleared for normal operation.
Bit 7 to 0 are cleared on hardware or software reset.
Address 03: Quiet Code, write only. default: 10000000
Quiet Code
This register controls the output value of the receive data FIFO when data underflow occurs. The
value equal to the quiet code of the CODEC should be written into this register. When data underflow
occurs, value of this register is outputted to the CODEC.
This register is set to the default value on hardware reset and it is unaffected by software reset.
Address 04 - 06: transmit status, write only, no default value
STO[7:0]
STO[15:8]
STO[23:16]
The transmit status field is sent by the W9330F during all transmission frame. Value of the STO field
is defined by the system controller and is not interpreted by the W9330F.
The value of these registers are unaffected by hardware and software reset. They are undefined after
system power up.
Address 08 - 0A: received status, read only
STI[7:0]
STI[15:8]
STI[23:16]
The received status field stores the status value received from each receive frame. These registers
are updated at the beginning of each receive frame after the status is received. Value of the STI field
is defined by the system controller and is not interpreted by the W9330F.
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