- 您現在的位置：買賣IC網 > PDF目錄363908 > W942508CH-5 (WINBOND ELECTRONICS CORP) 8M x 4 BANKS x 8 BIT DDR SDRAM PDF資料下載
參數資料
| 型號： | W942508CH-5 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| 中文描述： | 32M X 8 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數： | 3/47頁 |
| 文件大?。?/td> | 1317K |
| 代理商： | W942508CH-5 |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
W942508CH
Publication Release Date: May 21, 2003
- 3 -
Revision A3
1. GENERAL DESCRIPTION
W942508CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 8,388,608 words
×
4 banks
×
8 bits. Using pipelined architecture and 0.13
μ
m
process technology, W942508CH delivers a data bandwidth of up to 400M words per second (-5). To
fully comply with the personal computer industrial standard, W942508CH is sorted into four speed
grades: -5, -6, -7, -75 The -5 is compliant to the 200MHz/CL2.5 & CL3 specification, The -6 is
compliant to the 166MHz/CL2.5 specification, the -7 is compliant to the 143MHz/CL2.5 or
DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification.
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and
CLK
signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942508CH is ideal for main memory in
high performance applications.
2. FEATURES
2.5V
±
0.2V Power Supply for DDR266
2.5V
±
0.2V Power Supply for DDR333
2.6V
±
0.1V Power Supply for DDR400
Up to 200 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and
CLK
)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
8K Refresh cycles / 64 mS
Interface: SSTL-2
Packaged in TSOP II 66-pin, 400 x 875mil, 0.65mm pin pitch
相關PDF資料 |
PDF描述 |
|---|---|
| W942508CH-6 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942516CH | 4M X 4 BANKS X 16 BIT DDR SDRAM |
| W946432AD | 512K X 4 BANKS X 32 BITS DDR SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942516AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16 BIT DDR SDRAM |
| W942516BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
發布緊急采購，3分鐘左右您將得到回復。