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參數(shù)資料
| 型號(hào)： | W942508CH |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| 中文描述： | 8米× 4銀行× 8位DDR SDRAM |
| 文件頁(yè)數(shù)： | 10/47頁(yè) |
| 文件大小： | 1317K |
| 代理商： | W942508CH |
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W942508CH
- 10 -
7.5 DC Characteristics
MAX.
SYM.
PARAMETER
-5
-6
-7
-75
UNIT
NOTES
I
DD0
OPERATING CURRENT: One Bank Active-Precharge; t
RC
=
t
RC
min; t
CK
= t
CK
min; DQ, DM and DQS inputs changing twice
per clock cycle; Address and control inputs changing once per
clock cycle
OPERATING CURRENT: One Bank Active-Read-Precharge;
Burst = 2; t
RC
= t
RC
min; CL = 2.5; t
CK
= t
CK
min; I
OUT
= 0 mA;
Address and control inputs changing once per clock cycle.
PRECHARGE-POWER-DOWN STANDBY CURRENT: All
Banks Idle; Power down mode; CKE < V
IL
max; t
CK
= t
CK
min;
Vin = V
REF
for DQ, DQS and DM
110
110
110
110
7
I
DD1
120
120
120
120
7, 9
I
DD2P
8
8
8
8
I
DD2F
IDLE FLOATING STANDBY CURRENT: CS > V
IH
min; All
Banks Idle; CKE > V
IH
min; Address and other control inputs
changing once per clock cycle; Vin = Vref for DQ, DQS and DM
45
45
45
40
7
I
DD2N
IDLE STANDBY CURRENT: CS > V
IH
min; All Banks Idle;
CKE > V
IH
min; t
CK
= t
CK
min; Address and other control inputs
changing once per clock cycle; Vin > V
IH
min or Vin < V
IL
max
for DQ, DQS and DM
45
45
45
40
7
I
DD2Q
IDLE QUIET STANDBY CURRENT: CS > V
IH
min; All Banks
Idle; CKE > V
IH
min; t
CK
= t
CK
min; Address and other control
inputs stable; Vin > V
REF
for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One Bank
Active; Power down mode; CKE < V
IL
max; t
CK
= t
CK
min
40
40
40
35
7
I
DD3P
20
20
20
20
I
DD3N
ACTIVE STANDBY CURRENT: CS > V
IH
min; CKE > V
IH
min; One Bank Active-Precharge; t
RC
= t
RAS
max; t
CK
= t
CK
min;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One Bank Active; Address and control inputs changing once
per clock cycle; CL=2.5; t
CK
= t
CK
min; I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Write; Continuous burst;
One Bank Active; Address and control inputs changing once
per clock cycle; CL = 2.5; t
CK
= t
CK
min; DQ, DM and DQS
inputs changing twice per clock cycle
AUTO REFRESH CURRENT: t
RC
= t
RFC
min
SELF REFRESH CURRENT: CKE < 0.2V
RANDOM READ CURRENT: 4 Banks Active Read with
activate every 20ns, Auto-Precharge Read every 20 nS; Burst =
4; t
RCD
= 3; I
OUT
= 0mA; DQ, DM and DQS inputs changing
twice per clock cycle; Address changing once per clock cycle
70
70
70
65
7
I
DD4R
165
165
165
155
7, 9
I
DD4W
165
165
165
155
7
I
DD5
I
DD6
190
9
190
9
190
9
190
9
7
I
DD7
270
270
270
270
mA
CK
CK
DQS
RANDOM READ CURRENT Timing
t
RCD
t
RC
t
CK = 10ns
(
I
DD7)
Row d
Row c
Col c
Row e
Row e
Col e
ADDRESS
Row d
Col d
Row f
Row q
Col f
READ
AP
ACT
READ
AP
COMMAND
READ
AP
ACT
ACT
READ
AP
ACT
DQ
Qa
Qb
Qb
Qb
Qb
Qc
Qc
Qc
Qc
Qd
Qd
Qd
Qd
Qe
Qe
Qa
Row h
ACT
Bank 0
Bank 1
Bank 2
Bank 3
Bank 2
Bank 0
Bank 1
Bank 3
Bank 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W942508CH-5 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942516CH | 4M X 4 BANKS X 16 BIT DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W942508CH-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942516AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16 BIT DDR SDRAM |
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