- 您現在的位置：買賣IC網 > PDF目錄363908 > W981216 (WINBOND ELECTRONICS CORP) 2M x 16 bit x 4 Banks SDRAM PDF資料下載
參數資料
| 型號： | W981216 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 2M x 16 bit x 4 Banks SDRAM |
| 中文描述： | 200萬× 16位× 4個銀行內存 |
| 文件頁數： | 13/44頁 |
| 文件大小： | 2173K |
| 代理商： | W981216 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
W981216AH
2M x 16 bit x 4 Banks SDRAM
Revision 1.0 Publication Release Date: March, 1999
- 13 -
Auto-Precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-
precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically
before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the
end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore,
use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge
operation has started, the bank cannot be reactivated until the Precharge time (t
RP
) has been satisfied. Issue of Auto-Precharge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-
Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst
write cycle. This delay is referred to as Write t
DPL
. The bank undergoing auto-precharge can not be reactivated until t
DPL
and t
RP
are
satisfied. This is referred to as t
DAL
, Data-in to Active delay (t
DAL
= t
DPL
+ t
RP
). When using the Auto-precharge Command, the
interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t
RAS
(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when
CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge
each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated
before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must
be greater than or equal to the Precharge time (t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to
keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except
CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation
and before the next command can be issued. This delay is equal to the RAS cycle time plus the Self Refresh exit time.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the
power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down
mode longer than the Refresh period (t
REF
) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next
rising clock edge, depending on t
CK
. The input buffers need to be enabled with CKE held high for a period equal to t
CES
(min) +
t
CK
(min).
相關PDF資料 |
PDF描述 |
|---|---|
| W981216AH | 2M x 16 bit x 4 Banks SDRAM |
| W981216BH | 2M x 4 BANKS x 16 BIT SDRAM |
| W981216AH-75 | x16 SDRAM |
| W981216AH-8H | x16 SDRAM |
| W981616BH | 512K ⅴ 2 BANKS ⅴ 16 BITS SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W981216AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M x 16 bit x 4 Banks SDRAM |
| W981216AH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W981216AH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x16 SDRAM |
| W981216BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M x 4 BANKS x 16 BIT SDRAM |
| W981216BH-75 | 制造商:Winbond Electronics Corp 功能描述:SDRAM, 8M x 16, 54 Pin, Plastic, TSOP |
發布緊急采購，3分鐘左右您將得到回復。