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參數(shù)資料
| 型號： | WEDPNF8M721V-1012BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 13/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1012BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M721V-XBX
Parameter
Symbol
-100
-125
Unit
Min
Max
Min
Max
Access time from CLK (pos. edge)
CL = 3
CL = 2
t
AC
t
AC
t
AH
t
AS
t
CH
t
CL
t
CK
t
CK
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ
t
HZ
t
LZ
t
OH
t
OH
N
t
RAS
t
RC
t
RCD
t
REF
t
REF
t
RFC
t
RP
t
RRD
t
T
7
7
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
—
ns
ns
Address hold time
Address setup time
CLK high-level width
CLK ow-level width
1
2
3
3
1
2
3
3
8
Clock cycle time (6)
CL = 3
CL = 2
10
13
1
2
1
2
1
2
10
1
2
1
2
1
2
CKE hold time
CKE setup time
CS, RAS, CAS, WE, DQM hold time
CS, RAS, CAS, WE, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3 (7)
CL = 2 (7)
7
7
6
6
Data-out ow-impedance time
Data-out hold time (load)
Data-out hold time (no oad) (8)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows) – Commercial, Industrial
Refresh period (4,096 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (9)
WRITE recovery time
1
3
1
3
1.8
50
70
20
1.8
45
68
20
120,000
120,000
64
16
64
16
70
20
15
0.3
70
20
16
0.3
1.2
1.2
(10)
(11)
t
WR
1 CLK + 7ns
15
80
1 CLK + 7ns
15
78
Exit SELF REFRESH to ACTIVE command
t
XSR
SDRAM E
LECTRICAL
C
HARACTERISTICS
A
ND
R
ECOMMENDED
AC O
PERATING
C
HARACTERISTICS
(N
OTES
1, 2, 3, 4, 5)
NOTES:
1. The minimum specifications are used only to ndicate cycle time at which
proper operation over the full temperature range s ensured.
2. An nitial pause of 100ms s required after power-up, followed by two AUTO
REFRESH commands, before proper device operation s ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement s exceeded.
3. n addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) n a monotonic manner
4. Outputs measured at 1.5V with equivalent oad:
5. AC timing and CC tests have VIL = 0V and VIH = 3V with timing referenced to
1.5V crossover point.
6. The clock frequency must remain constant (stable clock s defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, ncluding tWR, and PRECHARGE commands). CKE
may be used to reduce the data rate.
7. tHZ defines the time at which the output achieves the open circuit condition;
it s not a reference to VOH or VOL. The ast valid data element will meet tOH
before going High-Z.
8. Guaranteed by design, but not tested.
9. AC characteristics assume tT = 1ns.
10. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/
7ns after the first clock delay, after the ast WRITE s executed.
11. Precharge mode only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1012BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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