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參數資料
| 型號： | WEDPNF8M721V-1210BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 10/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1210BC |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
T
ABLE
2 - C
AS
L
ATENCY
F
IG
. 4 C
AS
L
ATENCY
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CAS
CAS
SPEED
LATENCY = 2
≤
75
≤
100
LATENCY = 3
≤
100
≤
125
-100
-125
accesses are single-location (nonburst) accesses.
COMMANDS
The Truth Table provides a quick reference of available com-
mands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to an SDRAM which is selected (CS is LOW). This pre-
n+m. The I/Os will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the rel-
evant access times are met, the data will be valid by clock
edge n + m For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the I/Os will start driving after T1 and the
data will be valid by T2. Table 2 indicates the operating fre-
quencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used be-
cause unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
相關PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1210BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WF128K16 | 5V FLASH MODULE |
| WF128K16-120CC5 | 5V FLASH MODULE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1210BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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