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參數(shù)資料
| 型號： | WEDPNF8M721V-1210BI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數(shù)： | 22/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1210BI |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
F
IG
. 7 E
RASE
O
PERATION
1. See Table 5 for erase command sequence.
2. See "FD3 : Sector Erase Timer" for more nformation.
Any commands written to the device during the Embed-
ded Program Algorithm are ignored. Note that a hardware
reset immediately terminates the programming operation.
The program command sequences should be reinitiated
once the device has reset to reading array data, to ensure
date integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation
and set FD5 to “1”, or cause the Data Polling algorithm to
indicate the operation was successful. However, a succeed-
ing read will show that the data is still “0”. Only erase op-
erations can convert a “0” to a “1”.
CHIP ERASE COMMAND SEQUENCE
Chip erase is six bus cycle operation. The chip erase com-
mand sequence is initiated by writing two unlock cycles,
followed by a setup command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not equire the system to preprogram prior to erase.
The Embedded Erase algorithm automatically programs and
verifies the entire memory for an all zero data pattern prior
to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 7
shows the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates the
operation. The Chip Erase command sequence should be
re-initiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase operation
by using FD7, FD6, or FD2, or RY/BY1. See “Write Operation
Status” for information on these status bits. When the Em-
bedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 7 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in “Flash AC Character-
istics” for parameters, and to Figure 13 for timings diagram.
SECTOR ERASE COMMAND
SEQUENCE
Sector erase is six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional un-
lock write cycles are then followed by the address of the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M721V-1210BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WF128K16 | 5V FLASH MODULE |
| WF128K16-120CC5 | 5V FLASH MODULE |
| WF128K16-120CC5A | 5V FLASH MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1210BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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