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參數資料
| 型號： | WEDPNF8M721V-1210BM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 12/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1210BM |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is
to be precharged, inputs BA0, BA1 select the bank. Other-
wise BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being is-
sued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the
READ or WRITE burst, except in the full-page burst mode,
where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in con-
ventional DRAMs. This command is nonpersistent, so it must
be issued each time a refresh is required.
The addressing is generated by the internal refresh control-
ler. This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each 128Mb SDRAM requires 4,096
AUTO REFRESH cycles every refresh period (tREF). Provid-
ing a distributed AUTO REFRESH command will meet the
refresh requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be is-
sued in a burst at the minimum cycle rate (tRC), once every
refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data in
the SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data with-
out external clocking. The SELF REFRESH command is initi-
ated like an AUTO REFRESH command except CKE is dis-
abled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care,”
with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. Once
CKE is HIGH, the SDRAM must have NOP commands is-
sued (a minimum of two clocks) for tXSR, because time is
required for the completion of any internal refresh in
progress.
Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
*Self refresh available n commercial and ndustrial temperatures only.
FLASH DESCRIPTION
The 8Mbit 3.3 volt-only Flash memory is organized as
1,048,576 bytes. The byte-wide (x8) data appears on FD0-
7; the word-wide (x16) data appears on FD0-15. This de-
vice requires only a single 3.3 volt Vcc supply to perform
read, program, and erase operations. A standard EPROM
programmer can also be used to program and erase the
device.
This device features unlock bypass programming and in-
system sector protection/unprotection.
This device offers access times of 100, 120 and 150ns, al-
lowing operation without wait states. To eliminate bus con-
tention the device has separate chip select (FCS), wite en-
able (FWE) and output enable (FOE) controls.
The device requires only a single 3.3 volt power supply for
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| WEDPNF8M721V-1212BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WF128K16 | 5V FLASH MODULE |
| WF128K16-120CC5 | 5V FLASH MODULE |
| WF128K16-120CC5A | 5V FLASH MODULE |
| WF128K16-120CI5 | 5V FLASH MODULE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1212BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1212BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1215BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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