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參數(shù)資料
| 型號(hào)： | AD7664ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 16-Bit, 570 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大小： | 392K |
| 代理商： | AD7664ASTRL |
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REV. 0
AD7664
–13–
of power supply sequencing and thus free from supply voltage
induced latchup. Additionally, it is very insensitive to power supply
variations over a wide frequency range as shown in Figure 9.
–
50
1
P
–
INPUT FREQUENCY
–
kHz
1000
–
60
–
70
–
80
100
–
55
–
65
–
75
10
Figure 9. PSRR vs. Frequency
POWER DISSIPATION VS. THROUGHPUT
Operating currents are very low during the acquisition phase,
which allows a significant power saving when the conversion
rate is reduced as shown in Figure 10. This power saving depends
on the mode used. In impulse mode, the AD7664 automatically
reduces its power consumption at the end of each conversion
phase. This feature makes the AD7664 ideal for very low power
battery applications. It should be noted that the digital inter-
face remains active even during the acquisition phase. To reduce
the operating digital supply currents even further, the digital
inputs need to be driven close to the power supply rails (i.e.,
DVDD or DGND for all inputs except EXT/
INT
, INVSYNC,
INVSCLK, RDC/SDIN, and OVDD or OGND for these last
four inputs).
100k
0.1
O
–
SAMPLING RATE
–
SPS
100k
1k
10
1
100
10k
1M
10k
1k
100
10
1
0.1
WARP/NORMAL
IMPULSE
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7664 is controlled by the signal
CNVST
which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST
signal operates independently of
CS
and
RD
signals.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 11. Basic Conversion Timing
In impulse mode, conversions can be automatically initiated. If
CNVST
is held low when BUSY is low, the AD7664 controls the
acquisition phase and then automatically initiates a new conver-
sion. By keeping
CNVST
low, the AD7664 keeps the conversion
process running by itself. It should be noted that the analog
input has to be settled when BUSY goes low. Also, at power-up,
CNVST
should be brought low once to initiate the conversion
process. In this mode, the AD7664 could sometimes run slightly
faster then the guaranteed limits in the impulse mode of 444 kSPS.
This feature does not exist in warp or normal modes.
t
9
t
8
RESET
DATA
BUSY
CNVST
Figure 12. RESET Timing
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical,
CNVST
signal
should have a very low jitter. Some solutions to achieve that is
to use a dedicated oscillator for
CNVST
generation or, at least,
to clock it with a high-frequency low-jitter clock as shown in
Figure 5.
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| AD7664ASTZ | 功能描述:IC ADC 16BIT UNIPOLAR 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤(pán)（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱(chēng):296-25851-6 |
| AD7664ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類(lèi)型:1 個(gè)單端，雙極 |
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