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| 型號： | AD7664ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 570 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 392K |
| 代理商： | AD7664ASTRL |
REV. 0
–3–
AD7664
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES (Continued)
Power Dissipation
7
570 kSPS Throughput
4
100 SPS Througput
6
In Power-Down Mode
7
97
21
115
mW
μ
W
μ
W
7
TEMPERATURE RANGE
8
Specified Performance
T
MIN
to T
MAX
–40
+85
°
C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15
μ
V.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In normal mode.
5
Tested in parallel reading mode.
6
In impulse mode.
7
With all digital inputs forced to OVDD or OGND respect
ively.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
Time Between Conversions
(Wrap Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
t
1
t
2
5
1.75/2/2.25
ns
μ
s
Note 1
t
3
t
4
25
1.5/1.75/2
ns
μ
s
t
5
t
6
t
7
2
ns
ns
μ
s
10
1.5/1.75/2
t
8
t
9
250
10
ns
ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figures 16 and 17 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
2
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
3
Internal SCLK LOW (INVSCLK Low)
3
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
10
1.5/1.75/2
μ
s
t
11
t
12
t
13
45
ns
ns
ns
40
50
5
t
14
t
15
t
16
t
17
10
10
10
ns
ns
ns
ns
25/275/525
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
4
40
30
9.5
4.5
3
3
ns
ns
ns
ns
ns
ns
75
10
10
10
2.75/3/3.25
ns
ns
ns
μ
s
t
29
1/1.25/1.5
μ
s
t
30
50
ns
(–40 C to +85 C, AVDD = DVDD
= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
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