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參數資料
| 型號： | AD7675 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 16位，100 kSPS的，差分ADC |
| 文件頁數： | 5/20頁 |
| 文件大小： | 399K |
| 代理商： | AD7675 |
REV. 0
AD7675
–
5
–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1
2
3, 6, 7,
40–42,
44–48
4
AGND
AVDD
NC
P
P
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
BYTESWAP
DI
Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Two’s Complement. When OB/
2C
is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these outputs are
in high impedance.
When SER/
PAR
is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus.
When SER/
PAR
is HIGH, EXT/
INT
is LOW and RDC/SDIN is LOW which is the serial
master read after convert mode. These inputs, part of the serial port, are used to slow down, if
desired, the internal serial clock which clocks the data output. In the other serial modes, these
inputs are not used.
When SER/
PAR
is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/
INT
tied LOW, the internal clock
is selected on SCLK output. With EXT/
INT
set to a logic HIGH, output data is synchronized
to an external clock signal connected to the SCLK input.
When SER/
PAR
is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
When SER/
PAR
is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT
.
When EXT/
INT
is HIGH, RDC/SDIN could be used as a data input to daisy chain the con-
version results from two or more ADCs onto a single SDOUTline. The digital data level on
SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence. When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/
SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data is output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground
5
OB/
2C
DI
8
SER/
PAR
DI
9, 10
DATA[0:1]
DO
11, 12
DATA[2:3] or
DI/O
DIVSCLK[0:1]
13
DATA[4]
or EXT/
INT
DI/O
14
DATA[5]
or INVSYNC
DI/O
15
DATA[6]
or INVSCLK
DI/O
16
DATA[7]
or RDC/SDIN
DI/O
17
18
OGND
OVDD
P
P
19
20
DVDD
DGND
P
P
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