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參數(shù)資料
| 型號： | AD7675 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 16位，100 kSPS的，差分ADC |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 399K |
| 代理商： | AD7675 |
REV. 0
AD7675
–
6
–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Type
Description
21
DATA[8]
or SDOUT
DO
When SER/
PAR
is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7675
provides the conversion result, MSB first, from its internal shift register. The DATA
format is determined by the logic level of OB/2C. In serial mode, when EXT/
INT
is LOW,
SDOUT is valid on both edges of SCLK. In serial mode, when EXT/
INT
is HIGH: If
INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling
edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
When SER/
PAR
is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless
of the state of SER/
PAR
.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
CS
is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7675. Current conversion if any is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
Start Conversion. If
CNVST
is HIGH when the acquisition phase (t
8
) is complete, the next
falling edge on
CNVST
puts the internal sample/hold into the hold state and initiates a
conversion. This mode is the most appropriate if low sampling jitter is desired. If
CNVST
is
LOW when the acquisition phase (t
8
) is complete, the internal sample/hold is put into the hold
state and a conversion is immediately started.
Must be tied to analog ground.
Reference Input Voltage
Reference Input Analog Ground
Differential Negative Analog Input
Differential Positive Analog Input
22
DATA[9]
or SCLK
DI/O
23
DATA[10]
or SYNC
DO
24
DATA[11]
or RDERROR
DO
25–28
DATA[12:15]
DO
29
BUSY
DO
30
31
32
DGND
RD
CS
P
DI
DI
33
34
RESET
PD
DI
DI
35
CNVST
DI
36
37
38
39
43
AGND
REF
REFGND
IN–
IN+
P
AI
AI
AI
AI
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
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