- 您現在的位置：買賣IC網 > PDF目錄373913 > AD7705BN (ANALOG DEVICES INC) ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% PDF資料下載
參數資料
| 型號： | AD7705BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AB, DIP-16 |
| 文件頁數： | 24/32頁 |
| 文件大小： | 264K |
| 代理商： | AD7705BN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD7705/AD7706
–24–
REV. A
Figures 16 and 17 show timing diagrams for interfacing to the
AD7705/AD7706 with
CS
used to decode the part. Figure 16 is
for a read operation from the AD7705/AD7706’s output shift
register while Figure 17 shows a write operation to the input
shift register. It is possible to read the same data twice from the
output register even though the
DRDY
line returns high after
the first read operation. Care must be taken, however, to ensure
that the read operations have been completed before the next
output update is about to take place.
The AD7705/AD7706 serial interface can operate in three-wire
mode by tying the
CS
input low. In this case, the SCLK, DIN
and DOUT lines are used to communicate with the AD7705/
AD7706 and the status of
DRDY
can be obtained by interrogat-
ing the MSB of the Communications Register. This scheme is
suitable for interfacing to microcontrollers. If
CS
is required as a
decoding signal, it can be generated from a port bit. For
microcontroller interfaces, it is recommended that the SCLK
idles high between data transfers.
The AD7705/AD7706 can also be operated with
CS
used as a
frame synchronization signal. This scheme is suitable for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by
CS
since
CS
would normally occur after the falling edge
of SCLK in DSPs. The SCLK can continue to run between
data transfers provided the timing numbers are obeyed.
DRDY
CS
t
3
t
4
t
6
t
7
t
5
t
10
t
9
t
8
SCLK
DOUT
MSB
LSB
Figure 16. Read Cycle Timing Diagram
CS
t
11
t
14
t
15
t
12
t
16
SCLK
DIN
MSB
LSB
t
13
Figure 17. Write Cycle Timing Diagram
The serial interface can be reset by exercising the
RESET
input
on the part. It can also be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7705/AD7706 DIN
line for at least 32 serial clock cycles the serial interface is reset.
This ensures that in three-wire systems, if the interface gets lost
either via a software error or by some glitch in the system, it can
be reset back to a known state. This state returns the interface
to where the AD7705/AD7706 is expecting a write operation to
its Communications Register. This operation in itself does not
reset the contents of any registers but since the interface was
lost, the information written to any of the registers is unknown
and it is advisable to set up all registers again.
Some microprocessor or microcontroller serial interfaces have a
single serial data line. In this case, it is possible to connect the
AD7705/AD7706’s DATA OUT and DATA IN lines together
and connect them to the single data line of the processor. A
10 k
pull-up resistor should be used on this single data line. In
this case, if the interface gets lost, because the read and write
operations share the same line the procedure to reset it back to a
known state is somewhat different than previously described. It
requires a read operation of 24 serial clocks followed by a write
operation where a Logic 1 is written for at least 32 serial clock
cycles to ensure that the serial interface is back into a known
state.
相關PDF資料 |
PDF描述 |
|---|---|
| AD7705BR | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7705BRU | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7706 | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7706BN | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7706BR | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7705BNZ | 功能描述:IC ADC 16BIT 2CH 16-DIP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7705BNZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
| AD7705BR | 功能描述:IC ADC 16BIT 2CH 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7705BR-REEL | 功能描述:IC ADC 16BIT 2CH 16-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:16 采樣率（每秒）:45k 數據接口:串行 轉換器數目:2 功率耗散（最大）:315mW 電壓電源:模擬和數字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數目和類型:2 個單端，單極 |
| AD7705BR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 16-Pin SOIC W T/R |
發布緊急采購，3分鐘左右您將得到回復。