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參數資料

型號：	EP1K100FC484-3N
廠商：	Altera
文件頁數：	37/86頁
文件大小：	0K
描述：	IC ACEX 1K FPGA 100K 484-FBGA
產品培訓模塊：	Three Reasons to Use FPGA's in Industrial Designs
標準包裝：	60
系列：	ACEX-1K®
LAB/CLB數：	624
邏輯元件/單元數：	4992
RAM 位總計：	49152
輸入/輸出數：	333
門數：	257000
電源電壓：	2.375 V ~ 2.625 V
安裝類型：	表面貼裝
工作溫度：	0°C ~ 85°C
封裝/外殼：	484-BGA
供應商設備封裝：	484-FBGA（23x23）
其它名稱：	544-2368 EP1K100FC484-3N-ND

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

All ACEX 1K devices provide JTAG BST circuitry that complies with the

IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be

configured using the JTAG pins through the ByteBlasterMV or BitBlaster

download cable, or via hardware that uses the JamTM Standard Test and

Programming Language (STAPL), JEDEC standard JESD-71. JTAG

boundary-scan testing can be performed before or after configuration, but

not during configuration. ACEX 1K devices support the JTAG

instructions shown in Table 14.

The instruction register length of ACEX 1K devices is 10 bits. The

USERCODE register length in ACEX 1K devices is 32 bits; 7 bits are

determined by the user, and 25 bits are pre-determined. Tables 15 and 16

show the boundary-scan register length and device IDCODE information

for ACEX 1K devices.

Table 14. ACEX 1K JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD

Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation and permits an initial data pattern to be output at the device

pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDI and TDO pins, allowing the BST data

to pass synchronously through a selected device to adjacent devices during normal

operation.

USERCODE

Selects the user electronic signature (USERCODE) register and places it between the

TDI

and TDO pins, allowing the USERCODE to be serially shifted out of TDO.

IDCODE

Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE

to be serially shifted out of TDO.

ICR Instructions

These instructions are used when configuring an ACEX 1K device via JTAG ports using

a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or

Jam Byte-Code File (.jbc) via an embedded processor.

Table 15. ACEX 1K Boundary-Scan Register Length

Device

Boundary-Scan Register Length

EP1K10

438

EP1K30

690

EP1K50

798

EP1K100

1,050

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相關代理商/技術參數	參數描述
EP1K100FI2562	制造商:Altera Corporation 功能描述:
EP1K100FI256-2	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI256-2N	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI484-2	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 333 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI484-2N	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 333 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

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