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您現在的位置：買賣IC網 > PDF目錄22012 > EP1K100FC484-3N (Altera)IC ACEX 1K FPGA 100K 484-FBGA PDF資料下載

參數資料

型號：	EP1K100FC484-3N
廠商：	Altera
文件頁數：	9/86頁
文件大小：	0K
描述：	IC ACEX 1K FPGA 100K 484-FBGA
產品培訓模塊：	Three Reasons to Use FPGA's in Industrial Designs
標準包裝：	60
系列：	ACEX-1K®
LAB/CLB數：	624
邏輯元件/單元數：	4992
RAM 位總計：	49152
輸入/輸出數：	333
門數：	257000
電源電壓：	2.375 V ~ 2.625 V
安裝類型：	表面貼裝
工作溫度：	0°C ~ 85°C
封裝/外殼：	484-BGA
供應商設備封裝：	484-FBGA（23x23）
其它名稱：	544-2368 EP1K100FC484-3N-ND

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Carry Chain

The carry chain provides a very fast (as low as 0.2 ns) carry-forward

function between LEs. The carry-in signal from a lower-order bit drives

forward into the higher-order bit via the carry chain, and feeds into both

the LUT and the next portion of the carry chain. This feature allows the

ACEX 1K architecture to efficiently implement high-speed counters,

adders, and comparators of arbitrary width. Carry chain logic can be

created automatically by the compiler during design processing, or

manually by the designer during design entry. Parameterized functions,

such as LPM and DesignWare functions, automatically take advantage of

carry chains.

Carry chains longer than eight LEs are automatically implemented by

linking LABs together. For enhanced fitting, a long carry chain skips

alternate LABs in a row. A carry chain longer than one LAB skips either

from even-numbered LAB to even-numbered LAB, or from odd-

numbered LAB to odd-numbered LAB. For example, the last LE of the

first LAB in a row carries to the first LE of the third LAB in the row. The

carry chain does not cross the EAB at the middle of the row. For instance,

in the EP1K50 device, the carry chain stops at the eighteenth LAB, and a

new carry chain begins at the nineteenth LAB.

Figure 9 shows how an n-bit full adder can be implemented in n +1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits

using the input signals and the carry-in signal; the sum is routed to the

output of the LE. The register can be bypassed for simple adders or used

for an accumulator function. Another portion of the LUT and the carry

chain logic generates the carry-out signal, which is routed directly to the

carry-in signal of the next-higher-order bit. The final carry-out signal is

routed to an LE, where it can be used as a general-purpose signal.

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相關代理商/技術參數	參數描述
EP1K100FI2562	制造商:Altera Corporation 功能描述:
EP1K100FI256-2	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI256-2N	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI484-2	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 333 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K100FI484-2N	功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 624 LABs 333 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256

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