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參數(shù)資料
| 型號(hào)： | EP1K50FC484-3 |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 12/86頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 484-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | ACEX-1K® |
| LAB/CLB數(shù)： | 360 |
| 邏輯元件/單元數(shù)： | 2880 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 249 |
| 門數(shù)： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA（23x23） |
| 其它名稱： | 544-1071 |
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2
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
–
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2
for 5.0-V operation
–
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
–
Operate with a 2.5-V internal supply voltage
–
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
–
ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
–
Built-in, low-skew clock distribution trees
–100% functional testing of all devices; test vectors or scan chains
are not required
–
Pull-up on I/O pins before and during configuration
■
Flexible interconnect
–FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Tri-state emulation that implements internal tri-state buses
–
Up to six global clock signals and four global clear signals
■
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Open-drain option on each I/O pin
–
Programmable output slew-rate control to reduce switching
noise
–Clamp to VCCIO user-selectable on a pin-by-pin basis
–
Supports hot-socketing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50FC484-3F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FC484-3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50FI256-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI256-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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