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參數(shù)資料

型號(hào)：	EP1K50FC484-3
廠商：	Altera
文件頁(yè)數(shù)：	67/86頁(yè)
文件大小：	0K
描述：	IC ACEX 1K FPGA 50K 484-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	60
系列：	ACEX-1K®
LAB/CLB數(shù)：	360
邏輯元件/單元數(shù)：	2880
RAM 位總計(jì)：	40960
輸入/輸出數(shù)：	249
門數(shù)：	199000
電源電壓：	2.375 V ~ 2.625 V
安裝類型：	表面貼裝
工作溫度：	0°C ~ 70°C
封裝/外殼：	484-BGA
供應(yīng)商設(shè)備封裝：	484-FBGA（23x23）
其它名稱：	544-1071

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

The logic array consists of logic array blocks (LABs). Each LAB contains

eight LEs and a local interconnect. An LE consists of a 4-input LUT, a

programmable flipflop, and dedicated signal paths for carry and cascade

functions. The eight LEs can be used to create medium-sized blocks of

logic—such as 8-bit counters, address decoders, or state machines—or

combined across LABs to create larger logic blocks. Each LAB represents

about 96 usable logic gates.

Signal interconnections within ACEX 1K devices (as well as to and from

device pins) are provided by the FastTrack Interconnect routing structure,

which is a series of fast, continuous row and column channels that run the

entire length and width of the device.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect routing structure. Each IOE

contains a bidirectional I/O buffer and a flipflop that can be used as either

an output or input register to feed input, output, or bidirectional signals.

When used with a dedicated clock pin, these registers provide exceptional

performance. As inputs, they provide setup times as low as 1.1 ns and

hold times of 0 ns. As outputs, these registers provide clock-to-output

times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG

BST support, slew-rate control, tri-state buffers, and open-drain outputs.

Figure 1 shows a block diagram of the ACEX 1K device architecture. Each

group of LEs is combined into an LAB; groups of LABs are arranged into

rows and columns. Each row also contains a single EAB. The LABs and

EABs are interconnected by the FastTrack Interconnect routing structure.

IOEs are located at the end of each row and column of the FastTrack

Interconnect routing structure.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EP1K50FC484-3F	制造商:未知廠家制造商全稱:未知廠家功能描述:Field Programmable Gate Array (FPGA)
EP1K50FC484-3N	功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - ACEX 1K 360 LABs 249 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K50FI256-1DX	制造商:未知廠家制造商全稱:未知廠家功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-1F	制造商:未知廠家制造商全稱:未知廠家功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI256-1P	制造商:未知廠家制造商全稱:未知廠家功能描述:Field Programmable Gate Array (FPGA)

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