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參數(shù)資料
| 型號(hào)： | EP1K50FC484-3N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 16/86頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 484-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | ACEX-1K® |
| LAB/CLB數(shù)： | 360 |
| 邏輯元件/單元數(shù)： | 2880 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 249 |
| 門(mén)數(shù)： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA（23x23） |
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Altera Corporation
23
ACEX 1K Programmable Logic Device Family Data Sheet
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Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
it supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used; one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1
implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the compiler automatically selects the best control
signal implementation. Because the clear and preset functions are active-
low, the Compiler automatically assigns a logic high to an unused clear or
preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
■
Asynchronous clear
■
Asynchronous preset
■
Asynchronous clear and preset
■
Asynchronous load with clear
■
Asynchronous load with preset
■
Asynchronous load without clear or preset
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| EP1K50FI256-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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