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參數資料
| 型號： | EP1K50QC208-2N |
| 廠商： | Altera |
| 文件頁數： | 25/86頁 |
| 文件大小： | 0K |
| 描述： | IC ACEX 1K FPGA 50K 208-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 144 |
| 系列： | ACEX-1K® |
| LAB/CLB數： | 360 |
| 邏輯元件/單元數： | 2880 |
| RAM 位總計： | 40960 |
| 輸入/輸出數： | 147 |
| 門數： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 544-1844 EP1K50QC208-2N-ND |
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Altera Corporation
31
ACEX 1K Programmable Logic Device Family Data Sheet
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On all ACEX 1K devices, the input path from the I/O pad to the FastTrack
Interconnect has a programmable delay element that can be used to
guarantee a zero hold time. Depending on the placement of the IOE
relative to what it is driving, the designer may choose to turn on the
programmable delay to ensure a zero hold time or turn it off to minimize
setup time. This feature is used to reduce setup time for complex pin-to-
register paths (e.g., PCI designs).
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices and provides up to 12 peripheral control signals that
can be allocated as follows:
■
Up to eight output enable signals
■
Up to six clock enable signals
■
Up to two clock signals
■
Up to two clear signals
If more than six clock-enable or eight output-enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chip-
wide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock, and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on an LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP1K50QC208-2P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50QC208-3F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50QC208-3N | 功能描述:FPGA - 現場可編程門陣列 FPGA - ACEX 1K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K50QI208-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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