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參數資料
| 型號： | EP4CE55F23C7N |
| 廠商： | Altera |
| 文件頁數： | 3/42頁 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV E FPGA 56K 484FBGA |
| 產品培訓模塊： | Designing an IP Surveillance Camera Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色產品： | Cyclone? IV FPGAs |
| 標準包裝： | 60 |
| 系列： | CYCLONE® IV E |
| LAB/CLB數： | 3491 |
| 邏輯元件/單元數： | 55856 |
| RAM 位總計： | 2396160 |
| 輸入/輸出數： | 324 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BGA |
| 供應商設備封裝： | 484-FBGA（23x23） |
| 其它名稱： | 544-2683 |
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Chapter 1: Cyclone IV Device Datasheet
1–11
Operating Conditions
December 2013
Altera Corporation
Internal Weak Pull-Up and Weak Pull-Down Resistor
Table 1–12 lists the weak pull-up and pull-down resistor values for Cyclone IV
devices.
Hot-Socketing
Table 1–13 lists the hot-socketing specifications for Cyclone IV devices.
1 During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin
capacitance is less than 20 pF.
Table 1–12. Internal Weak Pull
-Up and Weak Pull-Down Resistor Values for Cyclone IV Devices (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R_PU
Value of the I/O pin pull-up resistor
before and during configuration, as
well as user mode if you enable the
programmable pull-up resistor option
725
41
k
728
47
k
835
61
k
10
57
108
k
13
82
163
k
19
143
351
k
R_PD
Value of the I/O pin pull-down resistor
before and during configuration
619
30
k
622
36
k
625
43
k
735
71
k
8
50
112
k
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull
-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available
for JTAG TCK.
(2) Pin pull
-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) R_PU = (VCCIO –VI)/IR_PU
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = VCC + 5% – 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = 0 V;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
(4) R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO = VCC + 5%, VI = 50 mV;
Typical condition: 25°C; VCCIO = VCC, VI = VCC –5%;
Maximum condition: 100°C; VCCIO = VCC – 5%, VI = VCC – 5%; in which VI refers to the input voltage at the I/O pin.
Table 1–13. Hot
-Socketing Specifications for Cyclone IV Devices
Symbol
Parameter
Maximum
IIOPIN(DC)
DC current per I/O pin
300
A
IIOPIN(AC)
AC current per I/O pin
8 mA (1)
IXCVRTX(DC)
DC current per transceiver TX pin
100 mA
IXCVRRX(DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–13:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
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相關代理商/技術參數 |
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| EP4CE55F23C8 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55F23C8L | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55F23C8LN | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55F23C8N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55F23C9L | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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