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參數資料
| 型號： | EPF10K100EFC256-3 |
| 廠商： | Altera |
| 文件頁數： | 38/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 10KE FPGA 100K 256-FBGA |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 90 |
| 系列： | FLEX-10KE® |
| LAB/CLB數： | 624 |
| 邏輯元件/單元數： | 4992 |
| RAM 位總計： | 49152 |
| 輸入/輸出數： | 191 |
| 門數： | 257000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-FBGA（17x17） |
| 其它名稱： | 544-2192 |
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
PCI Pull-Up Clamping Diode Option
FLEX 10KE devices have a pull-up clamping diode on every I/O,
dedicated input, and dedicated clock pin. PCI clamping diodes clamp the
signal to the VCCIO value and are required for 3.3-V PCI compliance.
Clamping diodes can also be used to limit overshoot in other systems.
Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is
3.3 V, a pin that has the clamping diode option turned on can be driven by
a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When VCCIO is 2.5 V, a pin
that has the clamping diode option turned on can be driven by a 2.5-V
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can
be activated for a subset of pins, which would allow a device to bridge
between a 3.3-V PCI bus and a 5.0-V device.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast
slew rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew rate
pin-by-pin or assign a default slew rate to all pins on a device-wide basis.
The slow slew rate setting affects the falling edge of the output.
Open-Drain Output Option
FLEX 10KE devices provide an optional open-drain output (electrically
equivalent to open-collector output) for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
MultiVolt I/O Interface
The FLEX 10KE device architecture supports the MultiVolt I/O interface
feature, which allows FLEX 10KE devices in all packages to interface with
systems of differing supply voltages. These devices have one set of VCC
pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).
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| EPF10K100EFC256-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EFC256-3N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 191 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EFC484-1 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EFC484-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EFC484-1N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 338 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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