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參數資料
| 型號： | EPF10K100EQC240-3N |
| 廠商： | Altera |
| 文件頁數： | 11/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 10KE FPGA 100K 240-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 24 |
| 系列： | FLEX-10KE® |
| LAB/CLB數： | 624 |
| 邏輯元件/單元數： | 4992 |
| RAM 位總計： | 49152 |
| 輸入/輸出數： | 189 |
| 門數： | 257000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports
high-speed counters and adders and the cascade chain implements
wide-input functions with minimum delay. Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Intensive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
created automatically by the Altera Compiler during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from odd-
numbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EPF10K50E device, the carry chain stops at the eighteenth LAB and
a new one begins at the nineteenth LAB.
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| EPF10K100EQC240-3 | IC FLEX 10KE FPGA 100K 240-PQFP |
| DS1780E | IC CPU PERIPHERAL MON 24-TSSOP |
| EBC08DCAH | CONN EDGECARD 16POS R/A .100 SLD |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EPF10K100EQI208-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI208-2 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K100EQI208-2DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI208-3DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| EPF10K100EQI240-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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