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參數資料
| 型號： | EPF6024AQC208-3N |
| 廠商： | Altera |
| 文件頁數： | 4/52頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 24K 208-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 144 |
| 系列： | FLEX 6000 |
| LAB/CLB數： | 196 |
| 邏輯元件/單元數： | 1960 |
| 輸入/輸出數： | 171 |
| 門數： | 24000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 544-1957 EPF6024AQC208-3N-ND |
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12
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Cascade Chain
The cascade chain enables the FLEX 6000 architecture to implement very
wide fan-in functions. Adjacent LUTs can be used to implement portions
of the function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical
OR
gate (via De Morgan’s inversion) to connect the outputs of adjacent
LEs. Each additional LE provides four more inputs to the effective width
of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can
be created automatically by the Altera software during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
cascade chains for the appropriate functions.
A cascade chain implementing an AND gate can use the register in the last
LE; a cascade chain implementing an OR gate cannot use this register
because of the inversion required to implement the OR gate.
Because the first LE of an LAB can generate control signals for that LAB,
the first LE in each LAB is not included in cascade chains. Moreover,
cascade chains longer than nine bits are automatically implemented by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from an even-numbered LAB to another even-numbered
LAB, or from an odd-numbered LAB to another odd-numbered LAB. For
example, the last LE of the first LAB in a row cascades to the second LE of
the third LAB. The cascade chain does not cross the center of the row. For
example, in an EPF6016 device, the cascade chain stops at the 11th LAB in
a row and a new cascade chain begins at the 12th LAB.
Figure 6 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. In this example, functions of 4n variables are
implemented with n LEs. The cascade chain requires 3.4 ns to decode a
16-bit address.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EPF6024AQC240-1 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-1N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-2 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-2N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024AQC240-3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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