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| 型號(hào)： | GS8642Z72GC-300 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 1M X 72 ZBT SRAM, 5.5 ns, PBGA209 |
| 封裝： | 22 X 14 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209 |
| 文件頁(yè)數(shù)： | 22/34頁(yè) |
| 文件大小： | 872K |
| 代理商： | GS8642Z72GC-300 |
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GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
22/34
2004, GSI Technology
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E
ADV
W
Bn
A0–An
DQ
G
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
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| GS8642Z72GC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 5.5NS/3NS 209FBGA - Trays |
| GS8642Z72GC-300IV | 制造商:GSI Technology 功能描述:72MB S/DCD SYNCH BURST SRAM - Bulk |
| GS8642Z72GC-300V | 制造商:GSI Technology 功能描述:72MB S/DCD SYNCH BURST SRAM - Bulk |
| GS8642ZV18B | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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