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參數資料
| 型號： | GS9020ACFV |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| 中文描述： | GENLINX -商標二GS9020A串行數字視頻輸入處理器 |
| 文件頁數： | 10/31頁 |
| 文件大?。?/td> | 258K |
| 代理商： | GS9020ACFV |
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2. FLYWHEEL BLOCK
2.1 FVH Flywheel
The flywheel’s primary function is to provide accurate field,
vertical, and horizontal output signals in the presence of
noisy or error prone input data. Flywheel synchronization is
based on the TRS words in the incoming data stream. The
FVH flywheel synchronizes to the incoming data stream in
less than two fields once the incoming standard has been
detected. Once synchronized, the TRS words in the
incoming data stream and those generated by the flywheel
are constantly compared to ensure that the flywheel
remains synchronized.
Noise insensitivity is accomplished by re-synchronizing the
flywheel to the data stream only if it is not aligned for long
periods of time. For component signals, four mismatches
between the EAV signal in the incoming and flywheel
generated signals over a window of eight lines will trigger
the flywheel to begin re-synchronization. For composite
signals, re-synchronization is triggered by mismatches in
the TRS encoded line numbers or field bits for 7
consecutive lines.
The flywheel can be disabled by asserting the FLYWDIS
control signal HIGH. Disabling the flywheel will remove the
effective noise immunity. In this mode, FVH values will be
decoded directly from the incoming data stream rather than
being decoded from the flywheel. Note that when the
flywheel is disabled, TRS_BLANK and TRS_INSERT will not
function correctly if enabled. Therefore if the flywheel is
disabled then so should TRS_BLANK and TRS_INSERT.
FLYWDIS is available as an input pin and as a bit in the
HOSTIF write table.
The SWITCHFLYW control signal is used in applications
where the data input to the GS9020A is switched between
two synchronous signals. In this case, the two signals may
be slightly misaligned and would normally require the
flywheel to completely re-synchronize. In this scenario, the
re-synchronization time would be undesirable. Asserting the
SWITCHFLYW bit of the HOSTIF write table HIGH allows the
flywheel to re-synchronize to the new incoming signal at the
end of the switching line.
For this functionality to operate properly, the two signals
must both be in the active picture portion of the switching
line at the time of the switch.
2.2 Accurate FVH Timing Signals
The F[2:0] signals indicate the current field of the video
data. Three F bits are necessary to accommodate the
composite PAL standard which has 8 fields. The F[2:0] bits
are available on dedicated output pins and via the HOSTIF
read table. Figure 8a and 8b illustrate the position of the
F[2:0] transition within a line for component and composite
signals, respectively. For component standards only, F0 is
used to indicate fields 0 and 1. The lines on which the
transitions occur conform to the SMPTE standards.
For component signals, the horizontal (H) signal is HIGH
during the horizontal blanking region of the output signal,
from EAV to SAV inclusive. For composite signals, the H
signal remains HIGH only for the 3FF, 000, 000, 000, and
TRSID words. Figure 8a and 8b illustrate the H output signal
timing for component and composite signals, respectively.
The vertical (V) signal timing is dependent on the incoming
video standard and the VBLANKS/L control signal. The
VBLANKS/L signal is available as an input pin and via the
HOSTIF write table and should be set to indicate the form of
the incoming data stream. This allows the flywheel to
correctly structure the V bit for flywheel synchronization,
TRS insertion, and TRS error indication.
For component based standards, the transition of the V
output signal within a line is shown in Figure 8a. The line on
which the V output signal transitions from HIGH to LOW is
summarized in the table below. The lines on which the LOW
to HIGH transition occurs conform to the SMPTE standards.
PIN
LOGIC OPR
HOST BIT
FLYWDIS
OR
FLYWDIS
SWITCHFLYW
PIN
LOGIC OPR
HOST BIT
F[2:0]
F[2:0]
V
H
VBLANKS/L
AND
VBLANKS/L
STANDARD
VBLANKS/L=1
VBLANKS/L=0
NTSC 4:2:2 Component
(13.5MHz Y sampling)
9/272
19/282
NTSC 4:2:2 16x9 Widescreen
(18MHz Y sampling)
9/272
19/282
NTSC 4:4:4:4 Single Link
(13.5MHz Y sampling)
9/272
19/282
PAL 4:2:2 Component
(13.5MHz Y sampling)
22/335
22/335
PAL 4:2:2 16x9 Widescreen
(18MHz Y sampling)
22/335
22/335
PAL 4:4:4:4 Single Link
(13.5MHz Y sampling)
22/335
22/335
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| GS9020ACTVE3 | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9021A | GENLINX -TM II GS9021A EDH Coprocessor |
| GS9021ACFU | GENLINX -TM II GS9021A EDH Coprocessor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9020ACFVE3 | 制造商:Semtech Corporation 功能描述:Video Proc 5V 0.19A 80-Pin LQFP Tray 制造商:Semtech Corporation 功能描述:Serial Digital Video Input Processor |
| GS9020ACTV | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9020ACTVE3 | 制造商:Semtech Corporation 功能描述:Serial Digital Video Input Processor |
| GS9020-CFV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
| GS9020-CTV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
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