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參數資料
| 型號： | GS9020ACFV |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| 中文描述： | GENLINX -商標二GS9020A串行數字視頻輸入處理器 |
| 文件頁數： | 12/31頁 |
| 文件大小： | 258K |
| 代理商： | GS9020ACFV |
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Sticky error flags that detect an error for a field remain
asserted until a HOSTIF read is performed on those error
flags. Sticky mode allows the user to perform HOSTIF reads
on the error flags to detect if any errors have occurred since
the last read, and are particularly useful when a read
cannot be performed after every field. When STICKY IN is
asserted HIGH, the incoming flags and validity bits are in
sticky mode. When STICKY OUT is asserted HIGH, the
outgoing flags and the EDH_CHKSM bit are in sticky mode.
Note that the INTERRUPT signal is derived from these
signals so that it too becomes sticky. STICKY IN and
STICKY OUT are available in the HOSTIF write table. The
ERROR FLAGS and the EDH_CHKSM bit are sticky HIGH.
That is, once they are set HIGH, they remain HIGH until a
read operation. The Validity bits are sticky LOW. That is,
once they are set LOW, they remain LOW until a read
operation.
In some applications, the user may wish to insert user
defined EDH error flags into the outgoing EDH packet. The
desired outgoing error flags are written into the OVERWRITE
VALUES words of the HOSTIF write table and are placed in
the outgoing EDH packet when the corresponding
OVERWRITE CONTROL bit is asserted HIGH. See Table 2
for the HOSTIF Write Table.
The GS9020A also allows the user to overwrite the seven
reserved words of the OUTGOING EDH packet. When
RO_CTRL (Reserved Word Overwrite Control) is asserted
HIGH, the GS9020A overwrites the reserved words in the
OUTGOING EDH packet with those specified in the HOSTIF
write table. If RO_CTRL is LOW, the GS9020A does not alter
the reserved words. RO_CTRL is a control bit in the HOSTIF
write table. The reserved words of the INCOMING EDH
packet are also available via the HOSTIF read table.
3.2 CRC Calculation And Updating
Since the device has the potential of modifying the full-field
and active picture data with features like ITU-R-601 clipping
and TRS insertion, the full field and active picture CRC
values must be calculated for both the incoming and
outgoing data streams. The calculated CRC values based
on the incoming data stream are used for comparison with
the embedded CRC values. However, the calculated CRC
values based on the outgoing data stream are the ones
inserted into the data stream. As a result, the CRC values in
the outgoing data stream correctly reflect the contents of
the outgoing data stream.
The INCOMING FF and AP CRC values for the Full Field
(FF) and Active Picture (AP) regions can be read from the
HOSTIF read table. Similarly, the OUTGOING (calculated)
FF and AP CRC values for the Full Field and Active Picture
regions can be read from the HOSTIF read table.
3.3 Validity Bit
The VALIDITY (V) bits (as per SMPTE 165) present in the
incoming EDH packet are used to indicate whether the CRC
values are valid or invalid. If the V bit is HIGH, the CRC
value is considered valid. In this case, the incoming CRC
value is compared with the calculated CRC value to identify
errors. If the V bit is LOW, the incoming CRC is invalid and a
CRC comparison is not performed. If the device receives an
EDH packet with the V bit set LOW it behaves as follows:
1. EDH = 0 (Not asserted for an invalid CRC)
2. EDA = EDAin "OR" EDHin (EDA calculated as usual)
3. A new calculated CRC value replaces the invalid one in
the output EDH packet
4. The V bit will be set HIGH in the output EDH packet
5. Depending on whether one or both or FFV or APV is low,
the Unknown Error Status (UES) flag corresponding to
either FF or AP or both, is set HIGH in the output data.
(No CRC check could be performed, so the data may or
may not contain errors).
The incoming V bits for the Full Field and Active Picture
regions are available in the HOSTIF read table as FFV and
APV, respectively. Outgoing full field (FFV) and active
picture (APV) validity bits are set HIGH unless explicitly
over-written through the HOSTIF write table or the flag port.
PIN
LOGIC OPR
HOST BIT
INCOMING FF CRC
OUTGOING FF CRC
INCOMING AP CRC
OUTGOING AP CRC
PIN
LOGIC OPR
HOST BIT
FFV
APV
相關PDF資料 |
PDF描述 |
|---|---|
| GS9020ACFVE3 | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9020ACTV | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9020ACTVE3 | GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9021A | GENLINX -TM II GS9021A EDH Coprocessor |
| GS9021ACFU | GENLINX -TM II GS9021A EDH Coprocessor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9020ACFVE3 | 制造商:Semtech Corporation 功能描述:Video Proc 5V 0.19A 80-Pin LQFP Tray 制造商:Semtech Corporation 功能描述:Serial Digital Video Input Processor |
| GS9020ACTV | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GENLINX -TM II GS9020A Serial Digital Video Input Processor |
| GS9020ACTVE3 | 制造商:Semtech Corporation 功能描述:Serial Digital Video Input Processor |
| GS9020-CFV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
| GS9020-CTV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial Digital Video Input Processor |
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