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參數資料
| 型號： | GS9021ACFU |
| 廠商： | Gennum Corporation |
| 英文描述： | GENLINX -TM II GS9021A EDH Coprocessor |
| 中文描述： | GENLINX -商標二GS9021A硬腦膜外血腫協處理器 |
| 文件頁數： | 6/26頁 |
| 文件大小： | 245K |
| 代理商： | GS9021ACFU |
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DETAILED DESCRIPTION
The GS9021A EDH coprocessor consists of five major
blocks:
1. Data Input/Output Block (with automatic standard
detect)
2. Flywheel Block
3. EDH Block
4. Data Processing Block
5. Host Interface (HOSTIF) Block
The following convention is used to differentiate device pins
from HOST interface table bits.
LOGIC OPR (logic operator) gives the combinational
relationship (if one exists), between pins which also have a
corresponding HOST bit. This operator governs the signal
the GS9021A receives. The following is the list of possible
logic operators and their meaning.
1. DATA INPUT/OUTPUT BLOCK
1.1 Parallel Digital Video Data Inputs
Parallel digital video data is supplied to the GS9021A chip
via the DIN[9:0] input pins. The data is clocked into the
GS9021A by the rising edge of PCLKIN.
Eight input signal standards are supported: Composite,
4:2:2 Component with 13.5MHz Y sampling, 4:2:2 16 x 9
wide screen with 18 MHz Y sampling, and 4:4:4:4
Component Single Link with 13.5MHz Y sampling, all in
both NTSC and PAL formats (See Table 1). Both 8 and 10
bit inputs are supported. However, when using 8 bit data,
the 2 LSBs of the input must be tied to GND.
1.2 Parallel Clock Inputs
The PCLKIN pin is the input used to clock the video data
into the GS9021A, and serves as the reference to which all
synchronous inputs and outputs are timed. The following
table shows which pins are synchronous with PCLKIN and
which are not. Timing for synchronous I/O is found in
Figures 1 and 2.
PIN
LOGIC OPR
HOSTIF
XX
YY
LOGIC OPR
MEANING
AND
XX AND YY
OR
XX OR YY
>
XX takes precedence over YY
<
YY takes precedence over XX
PIN
LOGIC OPR
HOST BIT
DOUT[9:0]
PIN
LOGIC OPR
HOST BIT
PCLKIN
SYNCHRONOUS
ASYNCHRONOUS
FL[4:0]
P[7:5]
S[1:0]
SCL/P4
FIFO_RESET
INTERRUPT
DOUT[9:0]
SDA/P3
F[2:0]
A[2:0]/P[2:0]
V
R/W
H
A/D
ANC_DATA
CS
BLANK_EN
FLAG_MAP
F_R/W
RESET
NO_EDH
CRC_MODE
STD[3:0]
VBLANKS/L
TRS_ERROR
HOSTIF_MODE
DIN[9:0]
FIFOE/S
FLYWDIS
BYPASS_EDH
SDO_MODE
ANC_CHKSM
CLIP_TRS
相關PDF資料 |
PDF描述 |
|---|---|
| GS9022-CPJ | Digital Video Serializer |
| GS9022 | Digital Video Serializer |
| GS9022-CTJ | Digital Video Serializer |
| GS9022ACPJE3 | GENLINXTM GS9022A Digital Video Serializer |
| GS9022ACTJE3 | GENLINXTM GS9022A Digital Video Serializer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9021ACFUE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:EDH Co-Processer |
| GS9021-CFU | 制造商:Gennum Corporation 功能描述: |
| GS9021-CTU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EDH Coprocessor |
| GS9022 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Video Serializer |
| GS9022A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serializer for SDI at 270-360Mb/s with Cable Driver |
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