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參數(shù)資料
| 型號： | KM68V1000BLT-7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| 中文描述： | 128K的× 8位低功耗和低電壓的CMOS Statinc內(nèi)存 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 183K |
| 代理商： | KM68V1000BLT-7 |
KM68V1000B, KM68U1000B Family
CMOS SRAM
Revision 2.0
March 1998
Address
Data Out
Previous Data Valid
Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
lL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
CS
1
Address
OE
Data ou
t
NOTES
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
CS
2
t
OH
t
AA
t
OLZ
t
LZ
t
OHZ
t
HZ(1,2)
t
RC
t
CO2
t
OE
t
CO1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM68V1000BLT-7L | 128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-7 | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| KM68V1000BLTE-7L | 128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM68V1000BLT-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-10L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
| KM68V1000BLTE-7L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128K X 8bit Low Power and Low Voltage CMOS Statinc RAM |
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