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參數(shù)資料
| 型號： | LA4032ZC-75TN48E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 40/42頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 32MACROCELLS 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LA-ispMACH |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
7
Block CLK3
PT Clock
PT Clock Inverted
Shared PT Clock
Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
PT Initialization/CE
PT Initialization/CE Inverted
Shared PT Clock
Logic High
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set
and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.
At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for
set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be
exchanged, providing exibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All ip-ops power up to a
known state for predictable system initialization. If a macrocell is congured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is congured to RESET on a
signal from the block-level initialization or is not congured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used
as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four
clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com-
binations of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
CLK1
CLK2
CLK3
Block CLK0
Block CLK1
Block CLK2
Block CLK3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LA4032ZC75TN48E-ACJ | 制造商:Lattice Semiconductor 功能描述:CUSTOM DEVICE FOR CONTINENTAL AUTOMOTIVE |
| LA4032ZV-75TN100E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZV-75TN128E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZV-75TN144E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZV-75TN44E | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
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