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參數資料
| 型號： | LMC6681BIM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Low Voltage, Rail-To-Rail Input and Output CMOS |
| 中文描述： | OP-AMP, 3000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁數： | 15/24頁 |
| 文件大小： | 750K |
| 代理商： | LMC6681BIM |
4.0 Capacitive Load Tolerance
(Continued)
The pulse response of the circuit shown in Figure 9 is shown in Figure 10
Application Hints
5.0 Printed-Circuit-Board Layout for High-Impedance Work
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low input current of the LMC6681/2/4, typically
less than 80 fA, it is essential to have an excellent layout.
Fortunately, the techniques of obtaining low leakages are
quite simple. First, the user must not ignore the surface leak-
age of the PC board, even though it may sometimes appear
acceptably low, because under conditions of high humidity or
dust or contamination, the surface leakage will be appre-
ciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6681/2/4’s inputs and
the terminals of capacitors, diodes, conductors, resistors, re-
lay terminals, etc. connected to the op-amp’s inputs, as in
Figure 11 To have a significant effect, guard rings should be
placed in both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 60 times degradation from the LMC6681/2/
4’s actual performance. However, if a guard ring is held
within 5 mV of the inputs, then even a resistance of 10
11
would cause only 0.05 pA of leakage current. See Figure 12
for typical connections of guard rings for standard op-amp
configurations.
DS012042-14
FIGURE 10. Pulse Response of the
LMC6682 Circuit Shown in
Figure 9
DS012042-18
FIGURE 11. Example of Guard Ring in PC Board
Layout
www.national.com
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| LMC6681BIN | Low Voltage, Rail-To-Rail Input and Output CMOS |
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| LMC6682AIMX | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6682AIN | Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6682BIM | Low Voltage, Rail-To-Rail Input and Output CMOS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LMC6681BIN | 制造商:Texas Instruments 功能描述: |
| LMC6682 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LMC6682AIM | 制造商:Texas Instruments 功能描述: |
| LMC6682AIMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage, Rail-To-Rail Input and Output CMOS |
| LMC6682AIN | 功能描述:IC OP AMP DUAL LO VOLT R-R 14DIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:1,000 系列:- 放大器類型:電壓反饋 電路數:4 輸出類型:滿擺幅 轉換速率:33 V/µs 增益帶寬積:20MHz -3db帶寬:30MHz 電流 - 輸入偏壓:2nA 電壓 - 輸入偏移:3000µV 電流 - 電源:2.5mA 電流 - 輸出 / 通道:30mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 16.5 V，±2.25 V ~ 8.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
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