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參數資料
| 型號： | LMC6684BIM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運算放大器 |
| 英文描述： | Low Voltage, Rail-To-Rail Input and Output CMOS |
| 中文描述： | QUAD OP-AMP, 3000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDSO16 |
| 封裝： | SOP-16 |
| 文件頁數： | 17/24頁 |
| 文件大小： | 750K |
| 代理商： | LMC6684BIM |
6.0 Powerdown
(Continued)
6.3 TEST CIRCUIT TO MEASURE t
ON
AND t
OFF
The circuit used to measure the t
, and t
during the
powerdown operation is a voltage follower with a load of
2 k
as shown in Figure 14
When the input to the powerdown pin is low, the LMC6681/
2/4 is on. Since the amplifier is connected in the voltage fol-
lower configuation, the output of the circuit is 1V. When the
powerdown pin is pulled high, the amplifier shuts down, and
draws less than 1 μA/Amplifier. In this powerdown mode, the
output pin has high impedance, and the output of the circuit
is pulled to 0V. t
is specified as the time between the 50%
points of the trailing edges of the input waveform at the pow-
erdown pin, and the waveform at the output pin. Similarly,
the t
is specified as the time between the 50% points of
the leading edges of the input waveform at the powerdown
pin, and the waveform at the output pin.
6.4 t
ON
and t
OFF
The t
(time delay for device to power on) the t
(time de-
lay for device to power off) specs are guaranteed at a supply
voltage of 3V. The t
and t
spec are independent of the
V
applied in the specified range. Refer to the Powerdown
DC Threshold Characteristics table for the values for a logic
low and a logic high.
The guaranteed spec for t
is 200 μs. This does not mean
that the signal to the V
PD
pin can be as high as 5 kHz (1/200
μs). Note that the V
frequency for the t
and t
mea-
surements is 5 Hz. The LMC6681/2/4 is ideal for DC type ap-
plications where the powerdown pin is controlled by low fre-
quency signals.
When the LMC6681/2/4 is powered off, internal bias currents
are shutoff. There is a inherent latency in the circuit, and the
device has to power off for a certain period of time for the t
spec to apply. Refer to the figure below. t
refers to the
time interval for which the device is in the powerdown mode.
Consider the case when the device has been powered off for
5 ms, and then the powerdown pin is pulled to a logic low.
From Figure 16 at room temperature, the device powers on
after 500 μs.
DS012042-16
FIGURE 14. Test Circuit for t
ON
and t
OFF
Measurements
DS012042-17
(a) t
OFF
Measurement
DS012042-29
(b) t
ON
Measurement
FIGURE 15.
DS012042-39
FIGURE 16. t
Delay Till Active-On after
t
PDOFF
in Powerdown Mode, V
S
= 3V
www.national.com
17
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