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參數資料
| 型號： | MC88915 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Skew CMOS PLL Clock Driver |
| 中文描述： | 低偏移的CMOS PLL時鐘驅動器 |
| 文件頁數： | 17/20頁 |
| 文件大小： | 216K |
| 代理商： | MC88915 |
MC88915TFN55/70/100/133/160
TIMING SOLUTIONS
BR1333 — Rev 6
17
MOTOROLA
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
47
BOARD VCC
0.1
μ
F (LOOP
FILTER CAP)
330
1M
0.1
μ
F HIGH
FREQ
BYPASS
10
μ
F LOW
FREQ BYPASS
47
BOARD GND
8
9
10
ANALOG VCC
RC1
ANALOG GND
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88915T
28–PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88915T IN A NORMAL
DIGITAL ENVIRONMENT.
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 6 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1b.The 47
resistors, the 10
μ
F low frequency bypass
capacitor, and the 0.1
μ
F high frequency bypass capacitor
form a wide bandwidth filter that will minimize the
88915T’s sensitivity to voltage transients from the system
digital VCC supply and ground planes. This filter will
typically ensure that a 100mV step deviation on the digital
VCC supply will cause no more than a 100pS phase
deviation on the 88915T outputs. A 250mV step deviation
on VCC using the recommended filter values should
cause no more than a 250pS phase deviation; if a 25
μ
F
bypass capacitor is used (instead of 10
μ
F) a 250mV VCC
step should cause no more than a 100pS phase
deviation.
If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88915T’s digital VCC supply. The
purpose of the bypass filtering scheme shown in Figure 6
is to give the 88915T additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.
1c.There are no special requirements set forth for the loop
filter resistors (1M
and 330
). The loop filter capacitor
(0.1
μ
F) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3
μ
A). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5M
reference
resistor should be used (instead of 1M
).
2. In addition to the bypass capacitors used in the analog
filter of Figure 6, there should be a 0.1
μ
F bypass
capacitor between each of the other (digital) four VCC pins
and the board ground plane. This will reduce output
switching noise caused by the 88915T outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the 88915T package as possible.
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| MC88915FN55PLCC | Low Skew CMOS PLL Clock Driver |
| MC88915T | LOW SKEW CMOS PLL CLOCK DRIVER |
| MC88915TFN133 | CONNECTOR ACCESSORY |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC88915EI55 | 功能描述:IC PLL CLOCK DRIVER 55MHZ 28PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MC88915EI55R2 | 功能描述:IC PLL CLOCK DRIVER 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MC88915EI70 | 功能描述:IC PLL CLOCK DRIVER 70MHZ 28PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MC88915EI70R2 | 功能描述:IC PLL CLOCK DRIVER 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MC88915FN55 | 功能描述:IC DRIVER CLK PLL 55MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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