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參數資料
| 型號： | MIC2310-2ZTS TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 13/34頁 |
| 文件大小： | 473K |
| 描述： | IC HOT SWAP CTLR 2CHAN 24TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電流限制： | 可調 |
| 電源電壓： | 10.8 V ~ 13.2 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC2310
July 2008
13
M9999-070108-A
Functional Description
Basic Startup Cycle
The basic operation of the MIC2310 is illustrated
below in Figure 2 from a cold-start condition. With the
applied V
CC
supply low such that the internal V
REG
voltage is less than the MIC2310s internal
V
VREG(UVLOH)
threshold voltage, all state machines are
reset, all voltage and current monitor subcircuits are
OFF, and the GATE drive circuit is disabled. Digital
inputs and all open-drain digital outputs are inactive.
When the applied V
CC
supply rises such that the
internal V
REG
voltage is above the controllers
V
VREG(UVLOH)
threshold voltage, the t
POR
counter circuit
commences. Once the timer terminates, all internal
state machines are activated, the CPRIMARY short
detection circuit is ON and the DG & DS MOSFET
short detection circuits are ON if ENABLE is LOW.
The I_FLT, PWRGD, and HW_FLT outputs are valid.
Upon the application of an ENABLE LOW-to-HIGH
transition after the t
POR
delay, or at the end of the t
POR
delay if ENABLE is already HIGH, a nominal start-up
commences where the dI
D
/dt-controlled inrush current
(by dI
D
/dt = 17.6x10
-3
? I
SLEW
/ (R
SENSE
證
SLEW
)) is
permitted to exceed the I
POC
threshold for t
POC
, until
there is sufficient charge stored on the load capacitor
as evidenced by the output load voltage profile. Note
that the secondary overcurrent detection threshold
(I
SOC
) is set externally at the controllers S[1:0] pins.
Once the inrush current exceeds the I
SOC
threshold,
the circuit breaker trips without delay and the
MIC2310 controller shuts down the output. If the
inrush current profile does not cause either of the OC
detection circuits to trip the circuit breaker and assert
the I_FLT digital output, the controller will assert the
PWRGD digital output when the output load voltage is
higher than the controllers V
PGH
threshold voltage and
the V
GS
of the external MOSFET is higher than the
controllers V
GSPGH
threshold voltage. Due to the low
R
DS(ON)
of the external MOSFET, the output load
voltage rises with the GATE voltage as the V
GS
of the
MOSFET reaches its threshold voltage. Once the
output load voltage stabilizes near the V
CC
supply
voltage, the V
GS
of the external MOSFET increases
above its threshold voltage and eventually exceeds
V
GSPGH
. The PWRGD output asserts to signal that the
external MOSFET is fully enhanced and ready for the
application of the full load.
V
CC
ENABLE
GATE
V
OUT
I
LOAD
I_FLT
PWRGD
Power
Good
Power
Not Good
0A
Primary & Secondary
OC Detector Armed
t
POR
I
SOC
= V
CBS
/R
SENSE
set by S[1:0]
t
POC
dI
D
/dt
Control
by C
SLEW
I
SOC
I
POC
I
POC
= V
CBP
/R
SENSE
+12V, nominal
V
REG
= 5V, nominal
Peak inrush current = f(C
SLEW
, C
LOAD
)
t
POC
= f(C
PRIMARY
)
t = f(C
GATE
,V
TH(FET)
)
V
GSPGH
VPGL
V
VREGUVLOH
V
GSPGH
Figure 2. Basic Startup Cycle
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