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參數(shù)資料
| 型號(hào)： | MIC2310-2ZTS TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 4/34頁 |
| 文件大小： | 473K |
| 描述： | IC HOT SWAP CTLR 2CHAN 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電流限制： | 可調(diào) |
| 電源電壓： | 10.8 V ~ 13.2 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
MIC2310
July 2008
4
M9999-070108-A
Pin Description
Pin Number
Pin Name
Pin Function
1
UVLO
Undervoltage Lockout Input. When the applied voltage at the UVLO pin is higher
than the controllers V
UVLOH
threshold voltage, the GATE drive circuits are active
when ENABLE= HIGH. If the applied voltage at the UVLO pin falls below the
controllers V
UVLOL
threshold voltage, the GATE drive circuits are disabled to turn
the external MOSFET OFF. In addition, the DISCH circuit is activated to drive an
optional, external discharge transistor alone (illustrated in the Typical Application
circuit) or in combination with an SCR for a very fast discharge circuit
configuration.
2
OVP
Overvoltage Protection Input. When the applied voltage at the OVP pin is higher
than the controllers V
OVPH
threshold voltage, the GATE drive circuit is disabled
to turn the external MOSFET OFF. In addition, the DISCH circuit is activated to
drive an optional, external discharge transistor alone (illustrated in the Typical
Application circuit) or in combination with an SCR for a very fast discharge circuit
configuration. Using an external resistor divider, the UVLO and the OVP pins
form a window comparator that defines the supply voltage range within which the
load may be safely powered.
3
VISS
Steady-state Output Current Monitor. This output signal provides an analog
voltage that is proportional to the steady-state load current. This signal is
provided as an input to the system supervisor/processor to monitor the dc
current/power level of the application circuit.
4
VREG
Internal +5V Regulator Bypass. Connect a 0.1-礔, 16V ceramic capacitor from
this pin to AGND.
5
NC
No connection
6
ENABLE
ENABLE Input. An active asserted-HIGH digital input that controls the operation
of the MIC2310. Activated after the internal POR timer has terminated, a LOW-
to-HIGH transition on this pin commences a start-up sequence if the applied V
CC
is above the V
UVLOH
and below the V
OVPH
threshold voltages. While ENABLE =
LOW, the GATE pin is held to 0V and the DISCH output is activated. The
ENABLE input can be used to reset the internal circuit breaker by applying a
HIGH-to-LOW-to-HIGH transition as defined by t
ENLPW
following either a load
current fault, an open LOADSENSE fault, an open GNDSENSE fault, or a
shorted RSENSE fault.
7
S0
8
S1
Secondary OC Detector Current Threshold Digital Inputs S1 is the MSB and
S0 is the LSB. When used together, S[1:0] sets the overcurrent threshold for the
secondary overcurrent detection circuit to one of four levels relative to the
primary overcurrent detector nominal threshold. For example, S[1:0] = L, L sets
the secondary overcurrent threshold at 1.3X; S[1:0] = L, H sets a 1.5X threshold;
S[1:0] = H, L sets a 2X threshold, and S[1:0] = H, H sets a 1.75X threshold. If the
S[1:0] pins are not connected or left NC, the default setting is S[1:0] = L, L or
1.3X. The permissible voltage range on these inputs is AGND d S[1:0] d V
CC
.
9
CRETRY
Auto-retry Timing Capacitor. A capacitor connected from the CRETRY pin to
AGND configures the MIC2310 to re-start automatically with ENABLE = HIGH
after the circuit breaker trips and latches off. It also sets the cool-off time delay
before a new load current start-up sequence is initiated. To configure the
MIC2310s circuit breaker to latch off after fault, connect this pin to AGND. The
circuit breaker latches OFF and remains latched OFF unless the ENABLE input
is toggled HIGH-to-LOW-to-HIGH as defined by t
ENLPW
or the V
CC
supply voltage
is turned OFF then ON.
10
CPRIMARY Primary Overcurrent Detector Timing Capacitor. Connecting a capacitor from the
CPRIMARY pin to AGND sets the response time of the controllers primary
overcurrent detection circuit to GATE OFF in the event of an overcurrent
condition. If the CPRIMARY pin is not connected, the primary overcurrent
detection response time defaults to t
POCSENSE
, typically 250祍 as specified in the
Electrical Characteristics Table. The controller incorporates a patent-pending
built-in test for a faulty CPRIMARY capacitor.
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