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參數資料
| 型號： | MSC7115VF1000 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 1/56頁 |
| 文件大小： | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 標準包裝： | 90 |
| 系列： | StarCore |
| 類型： | SC1400 內核 |
| 接口： | 主機接口，I²C，UART |
| 時鐘速率： | 266MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 400kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA |
| 供應商設備封裝： | 400-MAPBGA（17x17） |
| 包裝： | 托盤 |
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Freescale Semiconductor
Data Sheet
Document Number: MSC7115
Rev. 11, 4/2008
Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
MSC7115
MAP-BGA–400
17 mm
× 17 mm
StarCore SC1400 DSP extended core with one SC1400 DSP
core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
192 Kbyte M2 memory for critical data and temporary data
buffering.
8 Kbyte boot ROM.
AHB-Lite crossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
Internal PLL generates up to 266 MHz clock for the SC1400 core
and up to 133 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/
μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
UART with full-duplex operation up to 5.0 Mbps.
Up to 41 general-purpose input/output (GPIO) ports.
I2C interface that allows booting from EEPROM devices up to 1
Mbyte.
Two quad timer modules, each with sixteen configurable 16-bit
timers.
fieldBIST unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
Optional booting external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
Low-Cost 16-bit DSP with
DDR Controller
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相關代理商/技術參數 |
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|---|---|
| MSC7115VM1000 | 功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC7115VM800 | 功能描述:IC DSP PROCESSOR 16BIT 400MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:StarCore 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC7116 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7116_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7116VF1000 | 功能描述:數字信號處理器和控制器 - DSP, DSC 7116 STARLITE PB-BEARING RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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