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參數資料
| 型號： | TSB12LV26-EP |
| 英文描述： | 672-pin FineLine BGA |
| 中文描述： | 軍事增強塑料的OHCI -山貓基于PCI的1394主控制器 |
| 文件頁數： | 95/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26-EP |
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8
–
2
transfer. When the TSB41LV03A is in control of the D0
–
D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the TSB12LV32 is in control of the D0
–
D7 bus, unused Dn terminals are
ignored by the TSB41LV03A.
The LREQ terminal is controlled by the TSB12LV32 to send serial service requests to the Phy in order to
request access to the serial-bus for packet transmission, read or write Phy registers, or control arbitration
acceleration.
The LPS and LINKON terminals are used for power management of the Phy and TSB12LV32. The LPS
terminal indicates the power status of the TSB12LV32, and may be used to reset the Phy-LLC interface or
to disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the TSB12LV32 and
to indicate an interrupt to the TSB12LV32 when either LPS is inactive or the Phy register LCtrl bit is zero.
The DIRECT and ISO terminals are used to enable the output differentiation logic on the CTL0
–
CTL1 and
D0
–
D7 terminals. Output differentiation is required when an Annex J type isolation barrier is implemented
between the Phy and TSB12LV32.
The TSB41LV03A normally controls the CTL0
–
CTL1 and D0
–
D7 bidirectional buses. The TSB12LV32 is
allowed to drive these buses only after the TSB12LV32 has been granted permission to do so by the Phy.
There are four operations that may occur on the Phy-LLC interface: link service request, status transfer, data
transmit, and data receive. The TSB12LV32 issues a service request to read or write a Phy register, to
request the Phy to gain control of the serial-bus in order to transmit a packet, or to control arbitration
acceleration.
The Phy may initiate a status transfer either autonomously or in response to a register read request from
the TSB12LV32. The Phy initiates a receive operation whenever a packet is received from the serial-bus.
The Phy initiates a transmit operation after winning control of the serial-bus following a bus-request by the
TSB12LV32. The transmit operation is initiated when the Phy grants control of the interface to the
TSB12LV32.
The encoding of the CTL0
–
CTL1 bus is shown in Table 8
–
1 and Table 8
–
2.
Table 8
–
1. CTL Encoding When the Phy Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
No activity (this is the default mode)
0
1
Status
Status information is being sent from the Phy to the TSB12LV32.
1
0
Receive
An incoming packet is being sent from the Phy to the TSB12LV32.
1
1
Grant
The TSB12LV32 has been given control of the bus to send an outgoing packet.
Table 8
–
2. CTL Encoding When the TSB12LV32 Has Control of the Bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
The TSB12LV32 releases the bus (transmission has been completed)
0
1
Hold
The TSB12LV32 is holding the bus while data is being prepared for transmission, or
indicating that another packet is to be transmitted (concatenated) without arbitrating
1
0
Transmit
An outgoing packet is being sent from the TSB12LV32 to the Phy.
1
1
Reserved
Reserved
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| TSB12LV26IPZT | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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| TSB12LV26PZTG4 | 功能描述:1394 接口集成電路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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