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參數資料
| 型號： | W88113C |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | ATAPI的CD - ROM解碼器 |
| 文件頁數： | 61/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113C |
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W88113C
Publication Release Date: Mar. 1999
- 57 - Revision 0.61
DSTL - Decoding Sector Threshold Register - (write 81h)
If
DSCEN (80h.w6)
is enabled, this register specified the threshold number of successive sectors
minus one to be decoded after header is targeted. Flag
DSFULI (80h.r4)
becomes high when value
in
DSCL (81h,r)
is equal to
DSTL (81h,w)
at the end of EDC-checking. The initial value of
DSTL
(81h,w)
is FFh after chip reset, firmware reset and decoder reset. Note that threshold value should
not be set as 00h if
DSCEN (80h.w6)
is enabled.
DSTH - Obsolete (write 82h)
DSCL - Decoding Sector Counter - (read 81h)
Once the target header is found, this counter increments when a sector is completely decoded. This
counter is incremental-only, and the value follows FFh is 0. If
DSCEN (80h.6)
is high, flag
DSFULI
(80h.r4)
becomes high if
DSCL (81h,r)
is equal to
DSTL (81h,w)
at the end of EDC-checking.
Meanwhile, the decoder stops if
ASTOPb (80h.w3)
is low.
This register is cleared to 00h at the falling edge of
DECEN (0Ah,w7)
.
The initial value of DSCL after chip reset, firmware reset and decoder reset is 00h.
DSCH - Obsolete (read 82h)
TSL - Target Search Limit Register - (write 83h)
This register specified the limited number of target search. If
N
is the number specified by this
register,
TNFI (80h.r1)
becomes high if the headers have not match the target after
N
successive
sectors. Since this register will not be changed by decoding operation, there is no need to writing it
before every decoding operation. The initial value of TSL after chip reset, host reset and firmware
reset is FFh.
TSC - Target Search Counter - (read 83h)
After the decoder is enabled, the number of sectors has been searched can be monitored by reading
TSC. This register is cleared to 00h at the falling edge of
DECEN (0Ah,w7)
. The initial value of TSC
after chip reset, firmware reset and decoder reset is 00h.
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