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參數(shù)資料
| 型號(hào)： | W88113CD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | ATAPI CD-ROM DECODER & CONTROLLER |
| 中文描述： | IDE COMPATIBLE, CD ROM CONTROLLER, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 21/102頁 |
| 文件大小： | 573K |
| 代理商： | W88113CD |
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W88113C
Publication Release Date: Mar. 1999
- 17 - Revision 0.61
TACK - Transfer Acknowledge - (write 07h)
Writing this register deactivates flag
TENDb (01h.r6)
and its corresponding interrupt regardless of
what data is written.
HEAD0 to HEAD3 - Header Registers - (read 03h to 07h)
These four registers are used to hold the information of Header Bytes of each sector. Header
Registers should be read soon after
STAVAb (0Fh.r7)
becomes active-low. Note that the header
bytes are distrustful if wrong mode is set while ECC is enabled. If bit
SHDEN (0Bh.w0)
is enabled,
registers
HEAD0-3
are used to hold subheader bytes instead.
If control bit
QMSF (80h.w4)
is set high, the corresponding MSF bytes in Q-channel information
would be automatically loaded into
HEAD0-2 (04h-06h,r)
when each byte is ready from DSP.
Notice
that the value in register
HEAD3 (07h,r)
and
SUBH0-3 (14h-17h,r)
are not available in this case.
BIAL/BIAH - Buffering Initial Address - (write 08h/09h)
The rule for configuration is that the first byte of the sector is stored at
BIAH/L(09h/08h) - 0Ch
Before enabling the external RAM buffering through
CTRL0 (0Ah,w)
,
BIAH/L
should be set to control
the location of the first byte follows data sync for each data sector. The RAM block for buffering is
controlled by the number in registers
DDBH/L(29h/28h)
plus one. For convenience of following data
transfer, the microprocessor may set proper value to
BIAH/L
after the mode is determined so that the
first user data byte will locate at offset 00h of each data block.
CD-DA
yellow book
mode 1 & mode 2
CD-ROM XA
mode 2
BIAH/L(08h/09h)
000Ch
FFFCh
FFF4h
first sync
n/a
FFF0h
FFE8h
first header
n/a
FFFCh
FFF4h
first subheader
n/a
n/a
FFF8h
first data
0000h
0000h
0000h
BACL, BACH - Buffering Address Counter - (read 0Ah/0Bh)
After enabling the external RAM buffering, Buffering Write Counter is automatically increased by two,
beginning from the value specified by
BIAH/L (09h/08h,w)
, every time a data word is buffered.
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PDF描述 |
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| W88631F | VCD 4X RF Amplifer/Digital Servo & DSP(具有射頻運(yùn)算放大器及數(shù)字信號(hào)伺服和處理的集成芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W88113CF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:ATAPI CD-ROM DECODER & CONTROLLER |
| W88611P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88631F | 制造商:WINBOND 制造商全稱:Winbond 功能描述:VCD 4X RF AMP/DIGITAL SERVO & DSP |
| W88980 | 制造商:Performance Tool 功能描述:Anti-Fatigue Floor Mat Roll - 12 Square Feet 制造商:PERFORMANCE TOOLS 功能描述:ANTI-FATIGUE FLOOR MAT ROLL 12 SQ FT |
| W88981 | 制造商:Performance Tool 功能描述:Anti-Fatigue Floor Mat Roll - 32 Square Feet 制造商:PERFORMANCE TOOLS 功能描述:ANTI-FATIGUE FLOOR MAT ROLL 32 SQ FT |
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