
W88113C
Publication Release Date: Mar. 1999
Revision 0.61
- II -
5.2 MICROCONTROLLER INTERFACE..............................................................................................80
5.2.1 Direct Register Addressing .............................................................................................................80
5.2.2 General I/O.....................................................................................................................................81
5.2.3 Programmable System Clock ..........................................................................................................81
5.3 HOST INTERFACE............................................................................................................................83
5.3.1 Ultra DMA Mode Setting................................................................................................................83
5.3.2 Ultra DMA Data-out.......................................................................................................................83
5.3.3 Ultra DMA Error Handling.............................................................................................................84
5.3.4 Ultra DMA Data-In Transfer Diagram............................................................................................84
5.3.5 Data-in Transfer Flowchart Example..............................................................................................85
5.3.6 BSY Flag Control ..........................................................................................................................86
5.3.7 Pin HIRQ Control ..........................................................................................................................86
5.4 DECODER LOGIC.............................................................................................................................87
5.4.1 Sync Detection/Insertion.................................................................................................................87
5.4.2 Descramble.....................................................................................................................................87
5.4.3 Disk-Monitor Mode........................................................................................................................87
5.4.4 Parallel ECC Correction .................................................................................................................87
5.4.5 EDC Checking................................................................................................................................88
5.4.6 Real Time EDC Checking...............................................................................................................88
5.4.7 Decoding Sequence Model..............................................................................................................88
5.4.8 Disc Format Selection.....................................................................................................................88
5.4.9 CD-DA data & Q-channel Extraction .............................................................................................89
5.4.10 Target Search................................................................................................................................90
5.4.11 Automatic Header Comparison .....................................................................................................90
5.4.12 Status Collection...........................................................................................................................90
5.4.13 Decoder Processing Flow..............................................................................................................91
5.4.14 Buffer-Independent-Correction .....................................................................................................91
5.4.15 Remove Frequent SRIb & Automatic Cache Management ............................................................92
5.5 AUDIO-PLAYBACK..........................................................................................................................94
5.5.1 Configuration Phase........................................................................................................................94
5.5.2 Playback Phase ...............................................................................................................................94
5.5.3 IEC-958 Digital Audio Output........................................................................................................94
5.5.4 Audio Playback Flowchart Example................................................................................................95
6. ORDERING INSTRUCTION..................................................................................96
7. HOW TO READ THE TOP MARKING..................................................................96
8. PACKAGE DIMENSIONS.....................................................................................97