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參數資料
| 型號： | W88227F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 44/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227F |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 40 -
1999/10/1 Rev: 0.70
Bit 0:
SCIb - Subcode Interrupt Flag
If
SCIEN (2Ch.w4)
is enabled, this bit becomes active-low when one of the following events occurs:
ISS (22h.r0)
becomes active-high
NESBK (22h.r1)
becomes active-high
MSS (22h.r2)
becomes active-high
When Subcode Interrupt is activated, the microprocessor can read register
SUBSTA (22h,r)
to
determine the reason of interrupt. Writing register
SCIACK (22h,w)
deactivates this flag and its
corresponding interrupt.
TWCL - Transfer Word Counter Low- (read/write 02h)
Before triggering data transfer, the number of words to be transferred should be set through 12-bit Transfer
Word Counter (TWC). The number of
words
minus 1 should be written to this counter while using standard
ATAPI 16-bit data transfer. After host read one word, the counter is decreased by one.
Transfer End
Interrupt Flag
,
TENDb (01h.r6)
, is activated when this counter becomes zero.
Bit 7-0: TWCH[7:0] - Transfer Word Count Low
TWCH - Transfer Word Counter High - (read/write 03h)
Bit 7:
LATXF - Linear Address Transfer Enable
If this bit is high, the Linear Address Transfer is enabled. In this case, the data stored from the ddress
specified by
RAC (2Dh,1Dh,1Ch)
are transferred to host after trigger. The size of transfer data is
limited by
TWC (03h/02h)
.
If this bit is low, the Block-Offset Transfer is enabled. In this case, the data stored from the address
specified by
TBH/L (25h/24h)
and
TACH/L (05h/04h)
are transferred to host after trigger. The address
of data warps around at the block boundary, so the size of transfer data is limited by block size.
Bit 3-0: TWCH[3:0] - Transfer Word Count High
TACL/TACH - Transfer Address Counter - (write 04h/05h)
Before triggering block-offset data transfer, the external RAM address of data to be transferred should be set
through
TACH/L (05h/04h,w)
. This number in this counter specifies the first available data address relative to
the beginning of the block. The block number should also be specified through Transfer Block registers
TBH/L (25h/24h)
. After one word is read by host,
TACH/L
are incremented to the next available data address.
The following equation illustrates the relation between block-offset and linear address:
linear address = (block number
×
block size) + address offset
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