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參數資料
| 型號： | W88227QD |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數： | 73/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227QD |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 69 -
1999/10/1 Rev: 0.70
Bit 6:
CMDC - Command Conflict
This bit becomes high if one of the following events occurs while BSY is high:
Host writes any opcode to ATAPI Command Register while drive is selected.
Host writes any opcode to ATAPI Command Register while shadow drive is selected and
SHDRV
(3Fh.6)
is enabled.
Host writes opcode 90h (Execute Drive Diagnostics) to ATAPI Command Register.
CMDC is updated each time the host writes the ATAPI Command Register.
Bit 5:
TDIR - Data Transfer Direction
TENDb
(01h.r6)
TDIR
(30h.r5)
FPKT
(30h.1)
Transfer End
Reason
Acknowledge
register
Acknowledge Result
0
1
0
data-in transfer
DHTACK (0Eh)
TDIR is clear to 0
0
1
x
data-out transfer
TACK (07h)
TDIR is celar to 0 and
FPKT is unchanged
0
0
x
A0 command
packet transfer
TACK (07h)
This flag is cleared by writing
DHTACK (0Eh)
or writing
TACK (07h)
.
Bit 4:
Bit 3:
MBTI - Obsolete
UCRCOKB - Ultra DMA CRCOK/RAM Parity Interrupt Flag
This bit becomes high if an Ultra DMA CRC error is detected at the end of Ultra DMA burst. This
flag is clear to low by reading
MISS2 (30h.r)
.
Bit 2:
CRST - Chip Reset Flag
This bit is set high by chip reset. The first read of register
MISS2 (30h,r)
following the end of the
chip reset clears this flag to 0.
Bit 1:
FPKT -Full Packet Flag
This bit becomes high if the host has written the number of data bytes indicated in register ATBLO
(less than 12 bytes), or the host has written a 12-byte command packet. If CoD (32h.0) is low when
DRQ (37h.3) change from 0 to 1, the count in ATBLO is latched as a threshold value for FPKT logic.
If CoD is high when DRQ (37h.3) change from 0 to 1, the threshold value of FPKT logic is set as 12.
Whenever the number of bytes in the Packet
becomes high. To receive data from host using Packet FIFO, CoD (32h.0) and ATBLO (32h) should
be updated at rising edge of DRQ.
FIFO equals the threshold value, flag FPKT
Bit 0:
APKT - Automatic Packet Transfer Flag
This bit is set to 1 when host writes opcode A0h to ATA Command Register if drive is selected and
APKTEN (18h.7)
has been enabled. When this flag is high, BSY is controlled by the Automatic
Packet Transfer logic. Hence, setting of
CLRBSY (20h.4)
and
SETBSY (20h.4)
is of no effect. APKT
is de-activated by writing any value to register
TACK (07h,w)
. APKT is de-activated by master reset
but is not changed by firmware reset.
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