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參數資料
| 型號： | W89C880F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 1/26頁 |
| 文件大小： | 313K |
| 代理商： | W89C880F |
W89C880F FastMPR
100BASE-TX/T4 MULTIPORT
REPEATER CONTROLLER
Publication Release Date: January 1997
- 1 -
Revision A1
GENERAL DESCRIPTION
The W89C880F, a 100Base-T4/TX Fast Ethernet MultiPort Repeater Controller (FastMPR), is
designed for large Fast Ethernet networks. The W89C880F FastMPR complies fully with the
IEEE802.3u clause 27 repeater standard. The FastMPR offers a low-cost, high-performance solution
to alleviate the hub-to-network traffic distance limitation that Fast Ethernet faces. Two independent
MII ports are provided: a normal MII port that can support up to 11 PHY with the MII interface and an
extension port that can easily extend the distance between the hubs to as far as 100 meters. The
FastMPR implements a simple and limited bridge functions, such as address learning/filtering, runt
packet filtering, and two types of packet forwarding functions: fragment free and store-and-forward.
The extension port can be disabled by a hardware setting allowing it to act as a normal MII interface
port. The W89C880F offers a maximum of 12 ports. The device also supports one inter-FastMPR
interface to construct a large hub with up to 6 FastMPRs. The W89C880F implements enhanced
network status report functions, such as network utilization report, individual port partition status
report, individual port jabber status report, and collision report. The FastMPR also supports T4/TX and
translation mode, simultaneously connecting to a T4 or TX physical layer controller with the MII
interface.
FEATURES
Functions conform to IEEE802.3u clause 27 specifications
Supports up to 12 MII repeater ports
T4/TX translation function
Asynchronous inter-FastMPR interface for up to 6 FastMPR hub applications
A MII extension port with 100 meters hub-hub distance cascade capability
Limited bridge function: address learning/filtering, packet store/forwarding, fragment-free
32 KB
×
8, 64 KB
×
8, 128 KB
×
8 SRAM interface provided
MII management function supported
On-chip FIFO elasticity for physical signal retiming
Port status direct report function
On-chip network utilization report
Individual port, jabber/partition/reconnection state machine
Advanced CMOS process for lower power dissipation
Single 5V power supply
Packaged in 160-pin PQFP
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