
W921E840A/W921C840
Publication Release Date: July 1999
- 27 - Revision A3
D/A Converter MSB Data Register
DAMSB register: (address = 018H, default data = 0H)
b3
b2
b1
b0
6.10 Comparator
There are 4-channel inputs to the comparator negative (can be programmed to positive) terminal, but
only one channel will be active at a time. The control register is shown below.
ANIMUX register: (address = 019H, default data = 0H)
b3
b2
b1
b0
b0
0
1
0
1
b1
0
0
1
1
ANI0
ANI1
ANI2
ANI3
Enable
Reserved
Reserved
COMPTR register: (address = 01AH, default data = 4H)
b3
b2
b1
b0
0: Vpos voltage < Vneg voltage
1: Vpos voltage >= Vneg volatge
0: Compare stop
1: Compare start
(Read Only)
1: Vref = P5.3/DAOUT
0: Vref = P5.2/Vref
0: Vneg = Vref; Vpos = Vani
1: Vneg = Vani; Vpos = Vref
When the COMPTR register bit0 is set by software, the comparator starts and the bit2 of the
COMPTR register will be set to "1" initially. The comparing result will be stored in the bit2 of the
COMPTR register and will keep this value until the bit0 of the COMPTR register is set again. The only
way to disable the comparator is to reset the bit0 of the COMPTR register using the software control.
The initial value of the COMPTR bit2 is "1", the falling edge of COMPTR bit2 will cause the
comparator interrupt to become active if the enable flag of the comparator interrupt is set.
The bit3 of the COMPTR register controls the source of Input voltage reference (Vref). The input
reference voltage (Vref) comes from external pin (P5.2/Vref) or D/A converter analog signal output
(P5.3/DAOUT).