
W921E840A/W921C840
Publication Release Date: July 1999
- 37 - Revision A3
6.13 Operating Mode
There are three types of operating mode in this chip
normal mode, hold mode and stop mode.
6.13.1 Normal Mode
All functions works well and the
μ
C operates according to the clock generated by the system clock.
6.13.2 Hold Mode
In hold mode, all operations of
μ
C cease, except for the operation of the oscillator, timer/counter,
serial port and interrupt active pins. The
μ
C enters hold mode when the HOLD instruction is executed.
The hold mode can be released only by the RESET pin or the interrupt request signal. Before The
device enters the hold mode, the hold mode release flag1, 2, 3 (HMRF1, 2, 3, address = 036H, 037H,
038H) must be set to define the hold mode release conditions. If interrupt condition is met and
enabled in hold mode, the interrupt will be accepted to release hold mode and jump to interrupt vector
to execute interrupt service routine. For more details, refer to the following flags and flow chart.
HMRF1 register: (address = 036H, default data = 0H)
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LSB
MSB
7
8
9
A
B
C
D
E
F
1W/1C
1W/2C
1W/3C
2W/2C
2W/3C
3W/3C
Undecided
ADD A, #I
ADC A, #I
SUB A, #I
SBC A, #I
ANL A, #I
ORL A, #I
XRL A, #I
CMP A, #I
NOP
MOV B, A
MOV Mx, A
MOV @M A
MOV W, A
MOV V, A
MOV U, A
MOV A, B
MOV Mx, B
MOV @M B
MOV A, Mx
MOV B, Mx
MOV A, @M
MOV A, W
MOV A, V
MOV A, U
ADD A, Mx
ADC A, Mx
SUB A, Mx
SBC A, Mx
ADD A, @M
ADC A, @M
SUB A, @M
SBC A, @M
ANL A, Mx
ORL A, Mx
XRL A, Mx
CMP A, MX
ANL A, @M
ORL A, @M
XRL A, @M
CMP A, @M
INC B
DEC B
INC DP
DEC DP
CLRB Mx, bit
CLRB @M bit
SETB Mx, bit
SETB @M bit
CLR EVF
SET CF
MOV B, @M
SRL A
XCH A, B
SOP
SIP
RTN
RTNI
HOLD
STOP
SRH A
SLL A
SLH A
RRC A
RLC A
XCH V, CV
XCH U, CU
MOV DP, #I
XRL A, B
CMP A, B
CLR CF
HMRF2 register: (address = 037H, default data = 0H)
b3
b2
b1
b0
0: Serial port hold released disable
1: Serial port hold released enable
0: INT0 pin hold released disable
1: INT0 pin hold released enable
0: Comparator hold released disable
1: Comparator hold released enable
Reserved
HMRF3 register: (address = 038H, default data = 0H)
b3
b2
b1
b0
0: Pin P4.1 hold released disable
1: Pin P4.1 hold released enable
0: Pin P4.2 hold released disable
1: Pin P4.2 hold released enable
0: Pin P4.0 hold released disable
1: Pin P4.0 hold released enable
Reserved