
Preliminary W9321
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7.3.1. Transmit Path in the DSP Engine
A linear 14 bit sample input from the transmit path of the
Σ
Codec-filter block is sent in three
processing directions: sidetone gain process, Mu/A law compressor/Linear, and ADPCM encoder/
tone encoder. In the sidetone gain block, the input sample is fedback to the receive path and is
summed with the output of the digital receive gain. The value is kept in the -70 dB to -8.5 dB range by
the SSP port in BR1(b6:b4).The A/D output is then saved linearly into BR9(b7:b0) & BR10(b7:b2).
The ADPCM encoder/tone encoder provides 16 Kbps, 24 Kbps, or 32 Kbps ADPCM, or 64 Kbps PCM
respectively, as determined by the length of the transmit frame sync (pin 18). The length of the frame
sync is calculated by the number of falling edges at the BCLKT pin when the transmit frame sync FST
pin is high. Because the frame sync clock is 8 KHz, the encode interrupt is performed once every 125
μ
S.
As a default value the transmit ADPCM will be delayed by two frames after being requested, i.e. if the
current frame request is for ADPCM operation, it will be computed in the next frame and the ADPCM
result is transmitted in the next two frames. For applications such as the signaling channel of T1
frame structure the delay status can be configured to a total of 6 frames by the SSP port in BR7(b5).
The ADPCM output result will be sent to the serial data port (SDP) on the DT pin and the output data
rate from 128 KHz to 2048 KHz will be controlled by the serial data port on the BCLKT pin.
In the universal tone generator mode, the input of the ADPCM encoder comes from the output of the
universal tone generator, not from the transmit path in the
Σ
codec-filter. The ADPCM encoder
outputs the tone ADPCM signal through pin DT.
7.3.2. Receive Path in DSP Engine
The device receives data from the DR pin via the serial data port (SDP) under the control of the
BCLKR and FSR pins. The clock of the receive frame sync FSR is 8 KHz. The ADPCM decoder
receives one decode interrupt every 125
μ
S
. The serial data rate in the BCLKR is in the 128 KHz to
2048 KHz range. The input parameter data is sent to the ADPCM decoder which also provides 16
Kbps, 24 Kbps, or 32 Kbps ADPCM or 64 Kbps PCM, is determined by the length of the receive
frame sync FSR pin. The length of the frame sync is calculated by the number of falling edges at the
BCLKR pin when the receive frame sync FSR pin is high. The ADPCM decoder consists of a sync
adjustment operation for the correction of sync. tandem application, except when the receive digital
gain is used for a handset application. The digital receive gain is programmed from -12 dB to +12 dB
through the SSP port in BR3(b6:b0). In order to prevent noise from influencing the result of the
ADPCM decoder, the noise burst detection algorithm can be enabled by setting the BR7(b6) register
to detect interfering sounds and to mute the receive path.
The reconstructed linear PCM will be compressed by the Mu/A law compressor block and sent to
BR11 (b7:b0) on the SSP port after sync. adjustment in G.726 for CCITT test mode. After the control
of digital receive gain, the synthesized PCM data will be added to the feedback signal of the transmit
path in the sidetone gain block. The sum value is then passed to the Rx attenuation control block to
protect the output driver, RO, from distortion when the amplitude of the synthesis data is too large
(e.g. battery applications). The gain of the Rx. attenuation block is programmed through the BR2
(b2:b0) register in the SSP port. A receive attenuation range of from 0 to -7 dB can be programmed
in 1 dB steps.
If the device enables the universal tone generator, the function of the ADPCM decoder will be
disabled. Different tone types (i.e. tone 1 and tone 2) can be programmed through the BR7, BR4, and
BR5 registers in the SSP port. The tone generator can be used to generate DTMF tones, different
ringing tones, and call progress tones for handset applications. In telephone line applications, this
tone generator can be used for signaling on the line.