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參數資料
| 型號： | W942508CH-75 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M x 4 BANKS x 8 BIT DDR SDRAM |
| 中文描述： | 32M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數： | 2/47頁 |
| 文件大小： | 1317K |
| 代理商： | W942508CH-75 |
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W942508CH
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DM, DATA MASK (W942516CH).......................................................................................32
Mode Register Set (MRS) Timing......................................................................................33
Extend Mode Register Set (EMRS) Timing........................................................................34
Auto Precharge Timing (Read Cycle, CL = 2)....................................................................35
Auto Precharge Timing (Write Cycle).................................................................................37
Read Interrupted by Read (CL = 2, BL = 2, 4, 8)...............................................................38
Burst Read Stop (BL = 8)...................................................................................................38
Read Interrupted by Write & BST (BL = 8).........................................................................39
Read Interrupted by Precharge (BL = 8)............................................................................39
Write Interrupted by Write (BL = 2, 4, 8) ............................................................................40
Write Interrupted by Read (CL = 2, BL = 8) .......................................................................40
Write Interrupted by Read (CL = 2.5, BL = 4) ....................................................................41
Write Interrupted by Precharge (BL = 8)............................................................................41
2 Bank Interleave Read Operation (CL = 2, BL = 2)..........................................................42
2 Bank Interleave Read Operation (CL = 2, BL = 4)..........................................................42
4 Bank Interleave Read Operation (CL = 2, BL = 2)..........................................................43
4 Bank Interleave Read Operation (CL = 2, BL = 4)..........................................................43
Auto Refresh Cycle............................................................................................................44
Active Power Down Mode Entry and Exit Timing...............................................................44
Precharged Power Down Mode Entry and Exit Timing......................................................44
Self Refresh Entry and Exit Timing....................................................................................45
11.
PACKAGE DIMENSION ........................................................................................................... 46
11.1
TSOP 66l – 400 mil............................................................................................................46
12.
REVISION HISTORY................................................................................................................ 47
相關PDF資料 |
PDF描述 |
|---|---|
| W942516CH | 4M X 4 BANKS X 16 BIT DDR SDRAM |
| W946432AD | 512K X 4 BANKS X 32 BITS DDR SDRAM |
| W963A6BBN | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70 | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
| W963A6BBN70E | 512K WORD X 16 BIT LOW POWER PSEUDO SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W942516AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 16 BIT DDR SDRAM |
| W942516BH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM |
| W942516CH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BIT DDR SDRAM |
| W9425G6DH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M X 4 BANKS X 16 BITS DDR SDRAM |
| W9425G6EH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4 M 】 4 BANKS 】 16 BITS DDR SDRAM |
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