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參數資料
| 型號： | W981208AH-75 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | x8 SDRAM |
| 中文描述： | 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數： | 1/44頁 |
| 文件大小： | 2177K |
| 代理商： | W981208AH-75 |
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W981208AH
4M x 8 bit x 4 Banks SDRAM
Revision 1.0 Publication Release Date: March, 1999
- 1 -
Features
3.3V
±
0.3V power supply
Up to 133MHz clock frequency
4,194,304 words x 4 banks x 8 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Burst read, Single Writes Mode
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W981208AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 4M words x 4 banks x
8 bits. Using pipelined architecture and 0.20um process technology, W981208AH delivers a data bandwidth of up to 133M ( -
75) bytes per second. To fully comply to the personal computer industrial standard, W981208AH is sorted into two speed
grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W981208AH is ideal for main memory in high performance applications.
Key Parameters
Symbol
t
CK
Clock Cycle Time
t
AC
Access Time from CLK
t
RP
Precharge to Active Command
t
RCD
Active to Read/Write Command
I
CC1
Operation Current ( Single bank )
I
CC4
Burst Operation Current
I
CC6
Self-Refresh Current
Description
min/max
min
max
min
min
max
max
max
-75 (PC133)
7.5ns
5.4ns
20ns
20ns
85mA
120mA
2mA
-8H (PC100)
8ns
6ns
20ns
20ns
80mA
110mA
2mA
相關PDF資料 |
PDF描述 |
|---|---|
| W981208AH-8H | x8 SDRAM |
| W981208BH-7 | x8 SDRAM |
| W981208BH-75 | x8 SDRAM |
| W981208BH-8H | x8 SDRAM |
| W981216 | 2M x 16 bit x 4 Banks SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W981208AH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 8 BIT SDRAM |
| W981208BH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208BH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208BH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
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