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參數資料
| 型號： | WEDPNF8M721V-1012BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊多芯片封裝 |
| 文件頁數： | 14/42頁 |
| 文件大小： | 1276K |
| 代理商： | WEDPNF8M721V-1012BC |
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14
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M721V-XBX
NOTES:
1. The minimum specifications are used only to ndicate cycle time at which
proper operation over the full temperature range s ensured.
2. An nitial pause of 100ms s required after power-up, followed by two AUTO
REFRESH commands, before proper device operation s ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement s exceeded.
3. AC characteristics assume tT = 1ns.
4. n addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) n a monotonic manner
5. Outputs measured at 1.5V with equivalent oad:
SDRAM AC F
UNCTIONAL
C
HARACTERISTICS
(N
OTES
1,2,3,4,5,6)
Parameter/Condition
READ/WRITE command to READ/WRITE command (10)
Symbol
t
CCD
-100
1
-125
1
Units
t
CK
CKE to clock disable or power-down entry mode (7)
t
CKED
1
1
t
CK
CKE to clock enable or power-down exit setup mode (7)
t
PED
1
1
t
CK
DQM to nput data delay (10)
t
DQD
0
0
t
CK
DQM to data mask during WRITEs
t
DQM
0
0
t
CK
DQM to data high-impedance during READs
t
DQZ
2
2
t
CK
WRITE command to nput data delay (10)
t
DWD
0
0
t
CK
Data-in to ACTIVE command (8)
t
DAL
4
5
t
CK
Data-in to PRECHARGE command (9)
t
DPL
2
2
t
CK
Last data-in to burst STOP command (10)
t
BDL
1
1
t
CK
Last data-in to new READ/WRITE command (10)
t
CDL
1
1
t
CK
Last data-in to PRECHARGE command (9)
t
RDL
2
2
t
CK
LOAD MODE REGISTER command to ACTIVE or REFRESH command (11)
t
MRD
2
2
t
CK
Data-out to high-impedance from PRECHARGE command (10)
CL = 3
CL = 2
t
ROH
t
ROH
3
2
3
—
t
CK
t
CK
6. AC timing and CC tests have VIL = 0V and VIH = 3V with timing referenced to
1.5V crossover point.
7. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
8. Timing actually specified by tWR plus tRP; clock(s) specified as a reference
only at minimum cycle rate.
9. Timing actually specified by tWR.
10. Required clocks are specified by JEDEC functionality and are not dependent
on any timing parameter
11. JEDEC and PC100 specify three clocks.
相關PDF資料 |
PDF描述 |
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| WEDPNF8M721V-1012BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
相關代理商/技術參數 |
參數描述 |
|---|---|
| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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